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Method for calculating chip power consumption

A calculation method and power consumption technology, which is applied in the field of calculation of chip power consumption, can solve problems such as large errors and failure to consider the logic relationship of logic gates, etc.

Active Publication Date: 2012-10-10
PEKING UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] Method 1 does not consider the logical relationship between logic gates, so that for some specific logic gates, any permutation and combination of them can get the same calculation results, so the error is large

Method used

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  • Method for calculating chip power consumption
  • Method for calculating chip power consumption

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Embodiment Construction

[0028] The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0029] Such as Figure 1-2 As shown, a method for calculating chip power consumption according to the present invention includes the following steps:

[0030] A: Select a specific process and operating voltage, the logic gate standard cell under the process: such as two-input NAND gate NAND2, etc., under different input states (, , , ) Carrying out SPICE simulation can also obtain the sub-threshold leakage current of the logic gate standard cell under different input states;

[0031] B: According to the simulation results, a look-up table (Look-Up-Table) corresponding to the input state and leakage power consumption is established for each logic gate standard cell. For a...

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Abstract

The invention discloses a method for calculating chip power consumption. The method comprises the following steps: A, selecting the technology and the working voltage of a chip, and carrying out SPICE simulation on logic gate standard cells under the technology in different input states; B, according to a simulation result, for each logic gate standard cell, establishing a lookup table of the input states corresponding to leakage power consumptions; C, reading the logic gate in the circuit meshwork list of the chip, and determining that the logic gate input is the total input of the chip or the output of other logic gates; D, according to a determination result, calculating the probability of each input equal to (0) or (1) of the logic gate; E, according to the corresponding relation of the input states of the logic gate and leakage power consumptions and the probability of logic gate input states, calculating the leakage power consumption of the logic gate; and F, traversing the logic gates of the chip to obtain the leakage power consumption of each logic gate, and accumulating the obtained leakage power consumptions of the logic gates to obtain the leakage power consumption of the chip. The method of the invention can improve calculation accuracy of the chip power consumption based on a statistical sense.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuits, in particular to a method for calculating chip power consumption. Background technique [0002] At present, with the continuous reduction of the chip feature size, the leakage power consumption of the chip accounts for an increasing proportion of the total power consumption, and the leakage power consumption of the chip is mainly caused by the leakage current of the MOS transistor. MOS tube leakage current is mainly composed of subthreshold leakage current, gate oxide leakage current and substrate leakage current. The sub-threshold leakage current dominates the three types of leakage current, and the statistical calculation methods of the three currents are almost the same. Therefore, the calculation of the sub-threshold leakage current based on statistics has become the main part of the power consumption analysis. [0003] Statistical-based chip power analysis is a met...

Claims

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Application Information

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IPC IPC(8): G06F17/50G06F17/30
CPCY02D10/00
Inventor 杨小林杜刚刘晓彦张兴
Owner PEKING UNIV