Method for calculating chip power consumption
A calculation method and power consumption technology, which is applied in the field of calculation of chip power consumption, can solve problems such as large errors and failure to consider the logic relationship of logic gates, etc.
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[0028] The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.
[0029] Such as Figure 1-2 As shown, a method for calculating chip power consumption according to the present invention includes the following steps:
[0030] A: Select a specific process and operating voltage, the logic gate standard cell under the process: such as two-input NAND gate NAND2, etc., under different input states (, , , ) Carrying out SPICE simulation can also obtain the sub-threshold leakage current of the logic gate standard cell under different input states;
[0031] B: According to the simulation results, a look-up table (Look-Up-Table) corresponding to the input state and leakage power consumption is established for each logic gate standard cell. For a...
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