Method and framework for optimum grading of the inside of high performance static state random access memory

Abstract

The invention relates to a method for optimum grading of the inside of a high performance static state random access memory. The method includes inserting a trigger between an overall word line GWLL and a local word line LocalWLL and dividing each row of a storage array into N storage modules with equivalent storage units Bitcell. The framework for optimum grading of the inside of the high performance static state random access memory is further disclosed. The method and the framework reasonably select the number of N by discharging delay of Bitline, are capable of achieving approximate equality of the first grad and the second grade and achieve optimum performance accordingly. Suppose the storage module number of each row is N after word lines are graded, the total number of the storage units Bitcell of one row is T, if T=128, the word line grouping number N is larger than 1, and users can get the conclusion that the smaller the delay change on the overall word line GWLL is, the larger the grading number is, and delay of the local word line LocalWLL is greatly reduced. The inside word line grading framework is adopted, and the framework greatly reduces driving capability requirements for the trigger and simultaneously effectively reduces delay compared with the traditional framework.

Description

technical field [0001] The invention relates to the field of static random access memory, in particular to a method for internal optimal classification of high-performance static random access memory and its architecture. Background technique [0002] Static random access memory SRAM (Static Random Access Memory) is a volatile memory. It uses a bistable circuit as a storage unit. It can save the data stored in it without refreshing the circuit, and it works faster, so it is a computer system. A device that exchanges data directly with the CPU. Whether it is the cache cache in the mainframe or the register in the system-on-chip SOC, SRAM is an indispensable part for directly exchanging data with the CPU. [0003] SRAM is mainly composed of modules such as decoder, array read and write, timing control, and sensitive amplifier. Due to the limitation of area efficiency, it is difficult to control the delay of reading and writing of the decoder and array within 200ps. In order ...

AI Technical Summary

Problems solved by technology

The Cache in most Intel processors adopts multi-cycle read and write, which increases the clock speed, but the actual throughput does not increase

This is because multiple cycles of reading and writing are equivalent to controlling the SRAM after clock frequency division, and there is no change in the throughput of the SRAM.

Images