Semiconductor packaging member and manufacturing method
A semiconductor and packaging technology, which is applied in the field of semiconductor packaging with an electrical protective layer to improve yield, can solve the problems of increased cost, increased process time, complicated process, etc., and achieves the effect of reducing cost
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no. 1 example
[0054] see Figure 2A to Figure 2E , which is a schematic cross-sectional view of the manufacturing method of the first embodiment of the semiconductor package of the present invention.
[0055] Such as Figure 2A As shown, at first, a substrate 20 with opposite first surface 20a and second surface 20b is provided, and the first surface 20a defines a crystal placement M; then, through a patterning process, sputtering physical vapor deposition or The electrical protection layer 23 is formed on a portion of the second surface 20 b of the substrate 20 by chemical vapor deposition.
[0056]In this embodiment, the substrate 20 also has side surfaces 20c adjacent to the first and second surfaces 20a, 20b, such as the left and right side surfaces 20c as shown in the figure (may also include front and rear sides). side), and the material of the substrate and the patterning process are well known in the industry, so details are not repeated here.
[0057] In addition, the electrical...
no. 2 example
[0070] see Figure 3A to Figure 3D , which is the manufacturing method of the second embodiment of the semiconductor package of the present invention. The difference between the second embodiment and the first embodiment is that the structure of the substrate is different, and other related manufacturing processes are substantially the same, so the same manufacturing processes will not be repeated.
[0071] Such as Figure 3A As shown, the substrate 30 also has a groove 300 on the first surface 30a. In this embodiment, a through hole 301 is formed in the substrate 30 by etching first, so as to communicate with the bottom surface 300a of the groove 300 and the bottom surface of the substrate 30. The second surface 30b, and the die placement place M is located on a part of the bottom surface 300a of the groove 300, and the through hole 301 is located around the die placement place M.
[0072] Next, an electrical protection layer 33 with a thickness of about 0.3 μm is formed on...
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