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Semiconductor packaging member and manufacturing method

A semiconductor and packaging technology, which is applied in the field of semiconductor packaging with an electrical protective layer to improve yield, can solve the problems of increased cost, complicated process, increased process time, etc., and achieves the effect of reducing cost

Inactive Publication Date: 2015-04-08
SILICONWARE PRECISION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] However, in the existing LED packages, the main material of the substrate 10 is a binder, and the binder is mixed with zinc oxide particles. This process is too complicated, which leads to an increase in the process time and greatly increases the cost.

Method used

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  • Semiconductor packaging member and manufacturing method
  • Semiconductor packaging member and manufacturing method
  • Semiconductor packaging member and manufacturing method

Examples

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no. 1 example

[0054] see Figure 2A to Figure 2E , which is a schematic cross-sectional view of the manufacturing method of the first embodiment of the semiconductor package of the present invention.

[0055] Such as Figure 2A As shown, at first, a substrate 20 with opposite first surface 20a and second surface 20b is provided, and the first surface 20a defines a crystal placement M; then, through a patterning process, sputtering physical vapor deposition or The electrical protection layer 23 is formed on a portion of the second surface 20 b of the substrate 20 by chemical vapor deposition.

[0056]In this embodiment, the substrate 20 also has side surfaces 20c adjacent to the first and second surfaces 20a, 20b, such as the left and right side surfaces 20c as shown in the figure (may also include front and rear sides). side), and the material of the substrate and the patterning process are well known in the industry, so details are not repeated here.

[0057] In addition, the electrical...

no. 2 example

[0070] see Figure 3A to Figure 3D , which is the manufacturing method of the second embodiment of the semiconductor package of the present invention. The difference between the second embodiment and the first embodiment is that the structure of the substrate is different, and other related manufacturing processes are substantially the same, so the same manufacturing processes will not be repeated.

[0071] Such as Figure 3A As shown, the substrate 30 also has a groove 300 on the first surface 30a. In this embodiment, a through hole 301 is formed in the substrate 30 by etching first, so as to communicate with the bottom surface 300a of the groove 300 and the bottom surface of the substrate 30. The second surface 30b, and the die placement place M is located on a part of the bottom surface 300a of the groove 300, and the through hole 301 is located around the die placement place M.

[0072] Next, an electrical protection layer 33 with a thickness of about 0.3 μm is formed on...

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Abstract

Provided is a semiconductor packaging member and a manufacturing method. The semiconductor packaging member comprises a first surface possessing a substrate with a first circuit layer, a second circuit layer formed on the substrate and electrically connected to the first circuit layer, an electric protective layer formed on the second surface of the substrate and electrically connected to the second circuit layer, a chip arranged on the first surface of the substrate and electrically connected to the first circuit layer and a packaging rubber member formed on the substrate and clapping the chip. Accordingly, the electric protective layer is arranged on the second surface of the substrate and is in paralle connection with the chip in use to arrive the purpose of ESD electrostatic protection.

Description

technical field [0001] The invention relates to a semiconductor package, in particular to a semiconductor package with an electrical protection layer to improve yield. Background technique [0002] With the vigorous development of the electronic industry, electronic products tend to be thinner and smaller in form, and gradually enter the research and development direction of high performance, high function, and high speed in terms of function. Wherein, in light-emitting diode (Light-Emitting Diode, LED) devices, in order to avoid static electricity damage, most of them are equipped with ElectroStatic Discharge (ESD) structure. [0003] In current high-power LED packages, in order to achieve the purpose of static electricity protection, LED chips are connected in reverse parallel with Zener diodes (Zener Diodes) or Schottky diodes (Schottky Diodes) to avoid damage to LED chips caused by static electricity. Such as Figure 1A As shown, the Zener diode 13 and the LED chip 15 f...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L33/48H01L25/16H01C7/10H01L33/00
CPCH01L2924/12032H01L2924/3011H01L2224/48091H01L2224/73265H01L2224/48227H01L2224/32225H01L2924/00014H01L2924/00
Inventor 卢胜利王日富陈贤文杨贯榆王云汉
Owner SILICONWARE PRECISION IND CO LTD