Continuous time balance circuit applied to high-speed serial interface

Abstract

The invention discloses a continuous time balance circuit applied to a high-speed serial interface. The continuous time balance circuit comprises a programmable matching resistor module which is coupled to the ground, a continuous time balance amplifier circuit and an imbalance calibration module, wherein an external data signal is connected with the programmable matching resistor module through direct-current coupling or alternating-current coupling to generate locally received signals INN and INP; the signals are subjected to data balance through the continuous time balance amplifier, and meanwhile, direct-current level conversion is finished; the unbalanced data signals INN and INP which are referenced to the ground are converted into balance data signals OUTN and OUTP which are referenced to a power supply; and meanwhile, the system imbalance is measured by the imbalance calibration module; and the output Ioffsetn and the output Ioffsetp of the imbalance calibration module are regulated, so that the imbalance and removal are finished. According to the continuous time balance circuit, the three functions of level conversion, imbalance calibration and balance amplification of the data are realized by utilizing the continuous time balance amplifier at the same time; the error code rate of the data transmission is reduced; and the power consumption and the area of an integrated circuit are reduced.

Description

technical field [0001] The invention belongs to the technical field of data transmission and relates to a continuous time equalization circuit applied to a high-speed serial interface. Background technique [0002] In a high-speed serial interface, the transmitting end and the receiving end are each composed of a clock channel (optional) and one or more data channels. In the data path, it generally consists of an analog front-end module and a clock recovery data module. Among them, the analog front end is mainly composed of programmable matching resistors, equalizers, and decision devices. Because there is a certain high-frequency loss in the transmission channel in the high-speed serial interface application, the transmitted signal will have signal integrity problems and inter-symbol interference. Therefore, in the data path of the receiving end of the high-speed serial interface, the design of the equalizing amplifier is a very important module design. [0003] Among th...

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Problems solved by technology

[0005] The design of PMOS CML circuit in the prior art often requires larger power consumption and area

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