Structure and method to form a thermally stale silicide in narrow dimension gate stacks

Abstract

An integrated circuit is provided including a narrow gate stack having a width less than or equal to 65 nm, including a suicide region comprising Pt segregated in a region of the suicide away from the top surface of the suicide and towards an lower portion defined by a pulldown height of spacers on the sidewalls of the gate conductor. In a preferred embodiment, the spacers are pulled down prior to formation of the suicide. The suicide is first formed by a formation anneal, at a temperature in the range 250 DEG C to 450 DEG C. Subsequently, a segregation anneal at a temperature in the range 450 DEG C to 550 DEG C.; The distribution of the Pt along the vertical length of the suicide layer has a peak Pt concentration within the segregated region, and the segregated Pt region has a width at half the peak Pt concentration that is less than 50% of the distance between the top surface of the suicide layer and the pulldown spacer height.

Description

[0001] priority statement [0002] This application requires the U.S. patent application S / Priority of N: 12 / 611,946, the content of which patent S / N: 12 / 611,946 is hereby incorporated by reference in its entirety. technical field [0003] The present invention relates generally to the fabrication of integrated circuits, and in particular to Front-End of the Line (FEOL) processing, and more particularly to field-effect transistors (FETs) with narrow gate lengths. Method and structure for making silicide. Background technique [0004] The use of silicides as contact materials is well known in the manufacture of CMOS (Complementary Metal-Oxide Semiconductor) devices, such as FETs (Field Effect Transistors). Silicide provides FET source / drain regions and gate conductors with a material having relatively low sheet resistance, which also results in relatively low contact resistance. The low sheet resistance enables good current flow within the silicide, while the low contact ...

AI Technical Summary

Problems solved by technology

However, especially in devices with narrow (i.e., less than about 65 nm) gate dimensions, the Ni 1-x Pt x The upper part 155' of the silicide 155 tends to segregate Pt

This has the disadvantage of increasing the sheet resistance of the silicide

For example, 10% Pt will increase the sheet resistance of the silicide by about 50%

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