PROM circuit framework for FPGA configuration

Abstract

The invention discloses a PROM circuit framework for FPGA configuration. Through modular design, and increase of a peripheral circuit with specific functions, the FLASH memory is designed into a PROM circuit for storing FPGA configuration data and capable of adapting to requirements of different FPGA configuration modes, so as to finally complete independent configuration of the FPGA under a boundary scan mode, a serial mode or a parallel mode. The PROM using the circuit framework can be treated with capacity expansion through manner of cascade, and is compatible with an IEEE 1149.1 and an IEEE1532 boundary scan standard, so as to greatly enhance the flexibility of application oriented FPGA.

Description

technical field [0001] The invention relates to a PROM circuit architecture, in particular to a PROM circuit architecture optimized for FPGA configuration application, which belongs to the field of integrated circuits. Background technique [0002] figure 1 It is a schematic diagram of a configuration interface of a Field Programmable Gate Array (FPGA, Field Programmable Gate Array). Here, in order to illustrate the configuration principle of the FPGA100 device, only the interface signals related to the configuration are marked out, mainly including: configuration data input signal DIN[7:0], mode selection pin MODE PINS, FPGA configuration clock signal CCLK, configuration completion signal DONE, configuration initialization signal INITn, programming enable signal PROGRAMn, test data input signal TDI, test mode selection signal TMS, test clock signal TCK and test data output signal TDO. [0003] For the configuration of the FPGA100 device, generally there are three configur...

AI Technical Summary

Problems solved by technology

[0005] The technical solution problem of the present invention is: overcome the inadequacy of prior art, provide a kind of PROM circuit framework optimized for FPGA configuration application, solve the problem that traditional FLASH memorizer can't directly satisfy FPGA different configuration mode requirements, and Overcome the problem that the storage capacity of a single PROM chip is too small, which is not conducive to the expansion of configuration scale

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