Shifting register, a grid driver and a display device

A shift register and gate technology, which is applied in the field of gate drivers, display devices, and shift registers, can solve problems such as changes in threshold voltage, damage to the stability of shift registers, and wrong outputs, and achieve the effect of improving stability

Active Publication Date: 2013-01-09
HEFEI BOE OPTOELECTRONICS TECH +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] 1. How to reduce the capacitive coupling effect between the gate and drain of the pull-up TFT Tpu. If the charge accumulated on the gate of the TFT Tpu cannot be effectively released at the subsequent discharge moment, then as time accumulates, The coupling between the gate and the drain of the TFT Tpu will make the TFT Tpu turn on, then the output terminal Out_i will output the high level signal of CLK2 by mistake, which will destroy the stability of the shift register
[0008] 2. The gate of the pull-down TFT Tpd may be overbiased, causing the threshold voltage of the TFT Tpd to change
like figure 2 As shown, in order to make the output terminal Out_i output a low-level signal on VSS at a subsequent m

Method used

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  • Shifting register, a grid driver and a display device
  • Shifting register, a grid driver and a display device
  • Shifting register, a grid driver and a display device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0053] Such as Figure 4 Shown, in the shift register of the present embodiment:

[0054] The pull-up module includes: a first TFT T2 and a capacitor Cb, the gate of the TFT T2 is connected to the pull-up node PU, the drain is connected to the first clock signal input terminal CLK1, and the source is connected to the output terminal Out_i; the capacitor Cb is connected to the TFT T2 between the gate and source.

[0055] The pull-down module includes: a second TFT T6_P and a third TFT T6_N. The gate of TFT T6_P is connected to the first pull-down node PD_P, the drain is connected to the signal output terminal Out_i, and the source is connected to the low-level DC signal input terminal VSS; the gate of the third TFT T6_N is connected to the second pull-down node PD_N , the drain is connected to the signal output terminal Out_i, and the source is connected to the low-level DC signal input terminal VSS. When one of the pull-down nodes PD_P and PD_N is at a high level, TFT T6_P a...

Embodiment 2

[0075] Such as Figure 6 As shown, compared with the shift register of Embodiment 1, the shift register of this embodiment has removed the TFTs T7_P, T7_N and corresponding connecting wires. Its working sequence diagram and Figure 5 gives exactly the same, but relative to Figure 4 , the reduction of TFT T7_P, T7_N will be reduced in Figure 5 The degree of discharge to the nodes PD_P and PD_N at the beginning of the t0 time period shown in , the discharge to the nodes PD_P and PD_N in the t0 time period is completed by TFT T8_P and T8_N.

Embodiment 3

[0077] Such as Figure 7 As shown, compared with the shift register of Embodiment 1, the shift register of this embodiment has the sixteenth TFT T10_P added to the first pull-down control unit, and the seventeenth TFT T10_N and corresponding connections have been added to the second pull-down control unit Wire. Figure 8 The timing diagram of its work is given, and Figure 5 Compared to when the change occurs in time period t0, the level of PD_P is determined by Figure 5 given the high level becomes Figure 8 The low level shown, the other time periods are the same. This is due to the Figure 7 In , the gates of TFT T10_P and T10_N are connected to Out_i+1 terminal, in Figure 8 In the time period t2 shown, Out_i+1 is at a high level, so the TFTs T10_P and T10_N connected to the gate are both turned on, and the nodes PD_P and PD_N are connected to the low-level line VSS, so that the nodes PD_P and PD_N are both low level, even though CLK2 is at a high level at this time...

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Abstract

The invention discloses a shifting register, a grid driver and a display device and relates to the technical field of display. The shifting register comprises an upward-pulling module, a downward-pulling module and a control module, wherein the control module further comprises an upward-pulling control unit, a first downward-pulling control unit, a second downward-pulling control unit, a phase reversal unit and a reset control unit; and the upward-pulling module and the downward-pulling module transmit turn-off signals when signals input at a second clock signal input end by the first downward-pulling control unit and the second downward-pulling control unit are respectively high level and low level. The shifting register, the grid driver and the display device can effectively reduce the condenser coupling effect between a grid of an upward-pulling thin film transistor (TFT) and a leak and grid over bias voltage of a downward-pulling TFT, and further stability of the shifting register is effectively improved.

Description

technical field [0001] The invention relates to the field of display technology, in particular to a shift register, a gate driver and a display device. Background technique [0002] Liquid crystal displays (Liquid Crystal Display, LCD) are now widely used in various display fields, such as homes, public places, office places, and personal electronic related products. A liquid crystal display panel is usually mainly composed of a liquid crystal cell formed by an array substrate and a color filter substrate, a polarizer, and a backlight module. The array substrate is composed of a matrix of pixels in both horizontal and vertical directions. There are a large number of thin film transistors (Thin Film Transistor, TFT) formed by overlapping gate lines and data lines. The gate lines control the switching of the TFT. When the TFT is turned on, The pixel electrodes are charged or discharged through the data lines to control the magnitude of the voltage applied to the liquid crysta...

Claims

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Application Information

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IPC IPC(8): G11C19/28G09G3/20
Inventor 胡祖权邵贤杰王国磊马睿胡明
Owner HEFEI BOE OPTOELECTRONICS TECH
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