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Multiple-driver cross-connected memory testing device and application method thereof

A memory test and cross-connect technology, applied in the direction of instruments, static memory, etc., can solve the problems of lower test efficiency, increase the construction cost of test equipment, etc., and achieve the effect of reducing the number of components loaded

Inactive Publication Date: 2015-04-08
POWERTECH TECHNOLOGY
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, for the input / output pins of different bits, the current practice is that two sets of test fixtures must be prepared, and each driver is connected to the input / output pins of a fixed bit of the memory element to be tested with a fixed dedicated wire, according to Switching test fixtures for different specifications of pin transmission bits will not only increase the construction cost of test equipment, but also reduce test efficiency due to the switching of test fixtures when testing different bits

Method used

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  • Multiple-driver cross-connected memory testing device and application method thereof
  • Multiple-driver cross-connected memory testing device and application method thereof
  • Multiple-driver cross-connected memory testing device and application method thereof

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Embodiment Construction

[0034] Embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, but it should be noted that the accompanying drawings are simplified schematic diagrams, and are only used to illustrate the basic structure or implementation method of the present invention, so they only show the basic structure or implementation method of the present invention. The relevant elements and combinations are not intended to limit the present invention.

[0035] According to a specific embodiment of the present invention, a multi-driver cross-connected memory testing device is illustrated in Figure 1 to Figure 4Schematic diagram of different modes. The multi-driver cross-connected memory testing device of the present invention is used for testing the input / output pins of memory components, and is installed in a test fixture. The memory testing device includes a first pin wire bus 111, a second pin wire bus 112, a third pin wire bus 113, a ...

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Abstract

The invention relates to a multiple-driver cross-connected memory testing device, comprising: a first pin wire bus and a second pin wire bus which are connected with a first test region; a third pin wire bus and a fourth pin wire bus which are connected with the second test region; a first input / output drive module bus which is coupled with the first pin wire bus through a first drive wire bus; a first terminator bus which is coupled with the first drive wire bus through the first pin wire bus; a second input / output drive module bus which is coupled with the third pin wire bus through a second drive wire bus; and a second terminator bus which is coupled with the second drive wire bus through the second pin wire bus. According to the invention, the testing device disclosed herein can be applied for testing devices under test (DUT) of different input / output bits (e.g. 4-bit and 8-bit) without changing testing tools; in addition, test pattern signals can be synchronously written into a plurality of the DUTs and then read partitionedly, and there is no need for removing the DUTs and reducing the element loading amount in the test process.

Description

technical field [0001] The invention belongs to the technical field of testing semiconductor devices, in particular to a memory testing device with multiple drivers cross-connected. Background technique [0002] Memory is needed in various electronic products, among which DDR SDRAM is a kind of synchronous random access memory, which can support two data operations in each computer frequency cycle to increase the amount of data transmission. With the advancement of technology, DDR SDRAM memory has evolved to DDR2 and DDR3 or even higher, and its data transmission rate (Data Rate) has been increased from the early DDR 333 / 400 MH to DDR2 800MHz, DDR3 1333 MHz, and there will be more in the future. High data transfer rate. As the frequency increases, the test machine used to test the semiconductor memory must also be matched accordingly. [0003] The testing machine, for example: Advantest T5503 produced by Japan’s ADVANTEST CORPORATION, provides multiple test stations and ca...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/56
Inventor 叶志晖
Owner POWERTECH TECHNOLOGY
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