Address assignment method for data registers of distributed cache chipset

Abstract

The invention relates to an address assignment method for data registers of a distributed cache chipset. The address assignment method includes: a memory controller informs a central register through a command / address channel to start address assignment, then the central register informs all the data registers through a data control channel to prepare to receive address parameters through respective data channels, and the data registers receive and latch respective address parameters from the memory controller through the data channels. The defect that the data registers need multiple extra address pins to assign respective address data in the prior art, and size simplification of the data registers and the overall distributed cache chipset is influenced accordingly can be overcome.

Description

technical field [0001] The invention relates to a data buffer address allocation technology, in particular to a data buffer address allocation method applied in a distributed buffer chipset (Distributed Buffer Chipset). Background technique [0002] Today's computer systems require higher and higher memory (usually SDRAM) capacity. More memory means greater load and reduced signal integrity, so the memory capacity is limited. In order to increase the memory capacity of the system, a low-load dual in-line memory group (Load Reduced DIMM, LRDIMM) is designed, which inserts a buffer (Buffer) between the storage controller (Memory Controller) and the memory (such as SDRAM) to cache all The information, including commands, addresses and data, is driven by the storage controller to several registers, and then each register drives several memories, so the memory capacity is improved. [0003] At present, the buffer of LRDIMM is not necessarily a single chip, and some are distribut...

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Problems solved by technology

[0004] The configuration of the above address pins undoubtedly increases the overall size of the chip and also affects the size of the entire distributed cache chipset

However, in order to enhance market competitiveness, the existing computers are light, thin and small as the ultimate goal, so the distributed cache chipset configured in the computer must also develop in this direction, resulting in the distributed cache chipset packaged in the distributed cache chipset. The pin resources of the data register are also limited

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