Metal interconnection line manufacturing method

Abstract

The invention provides a metal interconnection line manufacturing method. The method includes: providing a semiconductor substrate and forming a dummy gate on the same; sequentially coating a stress layer and a first interlayer dielectric layer; exposing the dummy gate; removing the dummy gate to form a metal gate, and forming a metal oxide layer on the metal layer; sequentially forming the stress layer and the first interlayer dielectric layer on the side wall of the metal gate and on the semiconductor substrate, and forming the metal oxide layer on the metal gate; coating a second interlayer dielectric layer on the first interlayer dielectric layer and the metal oxide layer; forming openings and exposing the metal oxide layer and the stress layer in the openings; removing the metal oxide layer and the stress layer exposed in the openings; and forming a metal interconnection line in the openings. The method is used for protecting metal silicide regions in an active region and improving electric connection characteristics of the metal gate with the metal interconnection line and the active region with the metal interconnection line.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a method for manufacturing metal interconnection lines. Background technique [0002] As the integration of semiconductor devices becomes higher and higher, the voltage and current required for the operation of semiconductor devices continue to decrease, and the switching speed of transistors is also accelerated, and the requirements for various aspects of semiconductor technology have been greatly increased. The prior art process has made transistors and other types of semiconductor device components as thick as several molecules and atoms, and the materials that make up semiconductors have reached the limit of physical and electrical characteristics. [0003] As the gate process enters a new stage, the earliest part that reaches the limit is the gate oxide layer that makes up the semiconductor device, also known as the gate dielectric layer. The existing process ...

AI Technical Summary

Problems solved by technology

However, argon plasma beam sputtering will also remove the metal silicide region 13 located in the active region 11, reduce the thickness of the metal silicide region 13, and also affect the electrical extraction of the metal interconnection line to the active region 11, and also Occurrence of abnormal disconnection of semiconductor devices

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