Method and device for locking 64B/67B coding boundary
A boundary and coding technology, applied in the field of Ethernet, can solve the problems of difficult 32-bit input data to be spliced into 67-bit data output, inconsistency of 32-bit and 67-bit data, etc., to achieve the effect of fast conversion speed and simple logic control unit
Active Publication Date: 2015-05-13
SUZHOU CENTEC COMM CO LTD
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Problems solved by technology
However, in the prior art, the serial receiver cannot directly convert the received high-speed differential serial signal into parallel 67-bit wide data, but can only convert it into fixed-bit-width data, such as 32-bit wide
Due to the incommensurability of 32-bit and 67-bit, it is difficult to combine 32-bit input data into 67-bit data output in integer multiples
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[0040] The present invention will be described in detail below in conjunction with specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, method, or functional changes made by those skilled in the art according to these embodiments are included in the protection scope of the present invention.
[0041] Such as figure 1 As shown, it is a flowchart of a method for realizing 64B / 67B encoding boundary locking in a specific embodiment of the present invention, and the method includes the following steps:
[0042] S1. In each clock cycle, shift a 99-bit wide first shift register by 32 bits to the upper bits, and input a 32-bit first data to the lower 32 bits of the first shift register. It should be noted here that the clock cycle mentioned herein refers to a corresponding clock cycle for inputting 32-bit data, that is, in each clock cycle, an action of inputting 32-bit data is performed once.
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The invention provides a method for locking a 64B / 67B coding boundary. The method includes steps of offsetting a first shift register with a 99-bit width to a high order by 32 bits in each clock cycle, and inputting first 32-bit data to a low-order 32-bit position of the first shift register; controlling the interval of the clock cycles, extracting the offset quantity and extracting second 67-bit data from the first shift register; storing the second 67-bit data which are extracted from the first shift register twice in a second shift register with a 134-bit width; and determining an initial extracting address, starting from the initial extracting address to extract third 67-bit data in the second shift register, and locking a boundary of the third data. The method has the advantages that the 32-bit data which are inputted continuously are recovered into the effective 67-bit data meeting 64B / 67B coding requirements, the conversion speed is high, and logic control units are simple.
Description
technical field [0001] The invention relates to the technology in the field of Ethernet, in particular to a method and device for realizing 64B / 67B encoding boundary locking based on continuous 32-bit data input. Background technique [0002] At present, the huge application demand has promoted the rapid development of communication technology, and the communication rate has also increased. In order to improve the characteristics of data online transmission, the new generation of communication bus adopts serial data transmission, using 8B / 10B, 64B / 66B , 64B / 67B and other encoding methods to transmit data. [0003] Among them, the 64B / 67B encoding method is to add a 3-bit data control header on the basis of 64-bit data. The highest-bit data control header has an inversion feature, which can correct the original or near-error bits in a channel, and more Strict control of DC balance improves the reliability of data transmission on the system, and at the same time the utilizati...
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IPC IPC(8): H04L1/00
Inventor 耿磊
Owner SUZHOU CENTEC COMM CO LTD