Method and chip of increasing thickness of metal layer of chip bonding block area

Abstract

The invention discloses a method and a chip of increasing thickness of a metal layer of a chip bonding block area, so that the thickness of the metal layer of the chip bonding block area in the chip is increased, and the probability of punching the metal layer of the chip bonding block area in the process of wire bonding of the chip is lowered. The method of increasing the thickness of the metal layer of the chip bonding block area comprises the following steps. A passivation layer is deposited on a first metal layer of the chip, and the first metal layer covers a silicon substrate with the bonding block area; the passivation layer is coated with a photoetching glue layer; the photoetching glue layer is conducted with exposure and etching, and the photoresist in the bonding block area covering the chip is etched away; the passivation layer is conducted with isotropic etching, the passivation layer which covers the bonding block area and a part of the passivation layer which is covered by the photoetching glue layer are etched away, and the metal layer, covering the bonding block area, of the first metal layer is bared; second metal layers are generated on the photoetching glue layer and the metal layer which covers the bonding block area; stripping liquid is adopted to dissolve the photoetching glue layer so as to eliminate the photoetching glue layer and strip the metal layer which covers the photoetching glue layer.

Description

technical field [0001] The invention relates to the field of semiconductor chip manufacturing, in particular to a method for increasing the thickness of a metal layer in a chip pad area and a chip. Background technique [0002] At present, in the process of packaging the chip, it is necessary to wire the chip. The wire bonding position is mainly distributed on the pad area of ​​the chip. However, due to the thinner metal layer in the pad area, the wire bonding The problem that the metal layer (generally, the metal layer is an aluminum layer) is punctured is prone to occur in the system. [0003] With the development of chip packaging technology, because copper wire has the advantages of low price, low resistivity, high thermal conductivity and high hardness, copper wire is used as the wire material in the process of bonding chips; but copper The hardness of the wire is relatively high, so the thickness of the metal layer in the pad area of ​​the chip is required to be relat...

AI Technical Summary

Problems solved by technology

Using the existing solution, although the probability of the metal layer in the pad area being punctured during the wiring process can be reduced to a certain extent, after the metal layer of the chip is thickened, it will be difficult for the subsequent metal layer to be damaged during circuit wiring. Etching brings greater difficulty, and those skilled in the art should easily understand that in the case that the metal strip width / spacing is all the same, the thicker the metal layer is, the more difficult it is to etch the metal layer; therefore, in order to reduce the subsequent The difficulty of etching the metal layer during circuit wiring needs to be considered in compromise. In general, the thickness of the metal layer on the chip is increased by 10%; but because copper wires are used to wire the chip, only the metal layer If the thickness is increased by 10%, it still cannot meet the requirements of the metal layer and thickness of the copper wire on the pad area, and there is still the problem that the metal layer in the pad area is penetrated

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