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High electron mobility transistor and method of forming the same

A semiconductor, gate electrode technology, used in the field of formation of high electron mobility transistors and high electron mobility transistors

Active Publication Date: 2013-05-08
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition to the aforementioned adsorption properties, there are challenges associated with the development of devices based on III-V semiconductor compounds

Method used

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  • High electron mobility transistor and method of forming the same
  • High electron mobility transistor and method of forming the same
  • High electron mobility transistor and method of forming the same

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Embodiment Construction

[0030] The making and using of example embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are exemplary only, and do not limit the scope of the invention.

[0031] A plurality of semiconductor chip regions are marked above the substrate by scribe grooves between two chip regions. The substrate will go through multiple steps of cleaning, layering, patterning, etching and doping to form the integrated circuit. The term "substrate" generally refers herein to a bulk substrate on which various layers and device structures are formed. In some embodiments, the bulk substrate includes a silicon semiconductor or a compound semiconductor, eg, GaAs, InP, Si / Ge, or SiC. For example, these layers include dielectric layers, doped layers, polysilicon layers, or conductive layers. For example, devi...

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Abstract

A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode. The present invention also provides a high electron mobility transistor and a method of forming the same.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to US Provisional Patent Application Serial No. 61 / 553,510, filed October 31, 2011, the entire contents of which are hereby incorporated by reference. technical field [0003] The present invention relates generally to semiconductor structures and, more particularly, to high electron mobility transistors (HEMTs) and methods of forming high electron mobility transistors. Background technique [0004] In semiconductor technology, due to the characteristics of III-V (or III-V) semiconductor compounds, III-V (or III-V) semiconductor compounds are used to form various integrated circuit devices, such as High Power Field Effect Transistors, High Frequency Transistors or High Electron Mobility Transistors (HEMTs). Because HEMTs are typically metal-oxide-semiconductor field-effect transistors (MOSFETs), HEMTs are field-effect transistors that combine a junction (ie, a heterojunction) between t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/778H01L21/335
CPCH01L29/7787H01L29/517H01L29/66462H01L29/778H01L29/207H01L29/2003H01L29/7786H01L21/28264H01L29/513
Inventor 黄敬源游承儒姚福伟许竣为余俊磊熊志文杨富智
Owner TAIWAN SEMICON MFG CO LTD