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High voltage p-type ldmos structure and fabrication method thereof

A manufacturing method and high-voltage technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of unfavorable chip designers, increased costs, and sacrificed area, and achieve the effect of reducing the need for PNP punch-through and reducing the area

Active Publication Date: 2015-10-14
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
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  • Claims
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Problems solved by technology

But this increased cost and sacrificed area is not good for chip designers

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  • High voltage p-type ldmos structure and fabrication method thereof
  • High voltage p-type ldmos structure and fabrication method thereof

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Embodiment Construction

[0028] The cross-sectional view of an embodiment of the high-voltage P-type LDMOS structure of the present invention is as follows figure 2 As shown, area 1 is a PNP (P drift-DNW-P type substrate) structure in the vertical direction, and area 2 is an effective isolation area from the equipotential ring (guard ring) to the isolation ring (Isolation ring). A deep N well (Deep N well, DNW) is formed on the P-type silicon substrate, and an N well is formed in the left part of the deep N well, and a source terminal and a body terminal are formed on the N well. A P drift region is formed in the right part of the deep N well, and a drain terminal is formed on the P drift region. The left and right shallow N wells (shallow N well, SNW) are respectively formed adjacent to the left and right sides of the deep N well. and the right shallow N well, a P-type isolation ring (isolation ring) is formed on the left side of the left shallow N well and the right side of the right shallow N well...

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Abstract

The invention discloses a high-voltage P-type laterally diffused metal oxide semiconductor LDMOS structure. A deep N trap is formed in a P-type silicon substrate, an N trap is formed in the left portion of the deep N trap, a source end and a body end are formed on the N trap, a P drift region is formed in the right portion of the deep N trap, a drain end is formed on the P drift region, the left side of the deep N trap and the right side of the deep N trap are connected with each other and are respectively provided with a left side shallow N trap and a right side shallow N trap, P size insulating rings are respectively arranged on the left side of the left side shallow N trap and the right side of the right side shallow N trap. The invention further discloses the P-type LDMOS structure manufacturing method. The high-voltage P-type LDMOS structure and the high-voltage P-type LDMOS manufacturing method can sharply reduce the areas of the isolating rings and at the same time guarantee the problem of PNP punchthrough of the high-voltage P-type LDMOS device in the vertical direction.

Description

technical field [0001] The invention relates to semiconductor technology, in particular to a high-voltage P-type LDMOS structure and a manufacturing method thereof. Background technique [0002] The traditional structure of high-voltage P-type LDMOS (Lateral Double-Diffused Metal-Oxide Semiconductor Transistor) has a p-type well in the drain drift region (drain drift), and there will be a deep N-type well (Deep N well, DNW) implant under it, so as to For isolation purposes. Viewed in the vertical direction, a PNP (P drift-DNW-P type substrate) structure is formed, and its punch-through problem has always been a difficult point in the development of high-voltage PLDMOS devices. [0003] figure 1 It is a cross-sectional view of a traditional P-type LDMOS structure. Area 1 is a PNP (P drift-DNW-P type substrate) structure in the vertical direction. Area 2 is an effective isolation area from the equipotential ring (guard ring) to the isolation ring (Isolation ring). A deep ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06H01L21/336
Inventor 刘剑段文婷孙尧陈瑜陈华伦
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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