Method for upgrading firmware of CPLD (complex programmable logic device)

A technology for firmware upgrade and file upgrade, applied in the direction of program loading/starting, program control device, etc., to achieve the effect of low operating environment requirements and simple operation

Inactive Publication Date: 2013-05-22
SHANGHAI NORMAL UNIVERSITY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0011] The purpose of this invention is to provide a kind of method of CPLD firmware u

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  • Method for upgrading firmware of CPLD (complex programmable logic device)
  • Method for upgrading firmware of CPLD (complex programmable logic device)

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Embodiment Construction

[0021] In conjunction with the drawings, the present invention will be described below through specific embodiments.

[0022] figure 1 It is a block diagram of the probe device of the present invention. It includes a processor module, a memory module, a USB interface, 2 probes, a JTAG interface, and an internal rechargeable battery module. The device is used for the initialization of the probe and the simulation function of the signal. The device JTAG is connected to the target board, receives the relevant information of the target board, and synchronizes the clock information. The processor simulates one probe interface as the clock signal corresponding to the CPLD on the target board, and the other probe is used to transmit the upgrade file to the CPLD.

[0023] figure 2 It is the operation process of the present invention. The specific steps are:

[0024] A. The target board processor sets the CPLD to a programmable state.

[0025] B. Store the upgrade file in the pr...

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Abstract

The invention discloses a method for upgrading firmware of a CPLD (complex programmable logic device). The method is implemented by a programming device. The programming device comprises an embedded processor, at least one USB (universal serial bus) interface, a JTAG (joint test action group) port, two metal programming probes, a memory and a rechargeable battery, and the metal programming probes are connected with GPIO (general purpose input/output) ports of the embedded processor and are used for being in point connection with pins of the CPLD manually, so that a function of connecting clock signals with data signals is realized. The method includes enabling the target board processor to set the CPLD in a to-be-burnt programmable state; storing an upgrade file in the programming device via the USB interfaces; respectively butting the two metal programming probes to the pin CLK and the pin DATA of a target board; judging whether the programming device is correctly connected or not and matching equipment with the programming device; and transmitting the upgrade file to the CPLD to upgrade the firmware if the programming device is correctly connected.

Description

technical field [0001] The invention belongs to the field of embedded technology, in particular to a method for upgrading CPLD firmware. Background technique [0002] Today's society is a society where digitization and digital integrated circuits are widely used. Digital integrated circuits themselves are constantly being updated. It has developed from early tubes, transistors, small and medium-scale integrated circuits, to very large-scale integrated circuits (VLSIC, more than tens of thousands of gates), and many application-specific integrated circuits with specific functions. However, with the development of microelectronics technology, the task of designing and manufacturing integrated circuits is not completely undertaken by semiconductor manufacturers independently. System designers prefer to design application-specific integrated circuit (ASIC) chips by themselves, and hope that the ASIC design cycle is as short as possible. It is best to design a suitable ASIC chi...

Claims

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Application Information

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IPC IPC(8): G06F9/445
Inventor 杨敏
Owner SHANGHAI NORMAL UNIVERSITY
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