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A method for manufacturing a lightly doped drain region of a MOS transistor

A technology of MOS transistor and lightly doped drain region, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as cumbersome process flow, and achieve the effect of reducing process steps, manufacturing costs, and times.

Active Publication Date: 2016-03-30
FOUNDER MICROELECTRONICS INT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0021] The method and device provided by the present invention solve the problem of cumbersome technological process in the prior art

Method used

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  • A method for manufacturing a lightly doped drain region of a MOS transistor
  • A method for manufacturing a lightly doped drain region of a MOS transistor
  • A method for manufacturing a lightly doped drain region of a MOS transistor

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Embodiment Construction

[0050]An embodiment of the present invention provides a method for manufacturing a lightly doped drain region of a MOS transistor, which specifically includes: after forming a polysilicon gate, forming sidewalls on both sides of the polysilicon gate; covering the surface of the MOS transistor with photoresist to realize Perform photolithography on the source and drain of the MOS transistor to remove the photoresist in the active region; form an N-region by implanting phosphorus ions into the P well, and one side edge of the N-region extends below the sidewall; Implanting arsenic ions into the P well, wherein, when implanting the arsenic ions, the direction of implantation is perpendicular to the wafer; removing the photoresist on the surface of the MOS transistor; performing source-drain operation on the MOS transistor to make the The phosphorus ions are diffused from below the side wall to below the polysilicon gate to form an N-type lightly doped drain region, and the doped r...

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PUM

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Abstract

The invention discloses a metal oxide semiconductor (MOS) transistor lightly doped drain region manufacturing method. The MOS transistor lightly doped drain region manufacturing method is applied to the manufacturing field of semiconductor integrated circuits. The method comprises that flanks are manufactured on two sides of a polysilicon gate; photoetching is conducted to a drain source of a MOS transistor; phosphonium ions are implanted to form an N- region. Edges of one side of the N- region extend to the lower portion of the flank; arsenic ions are implanted, wherein the direction of arsenic ion implantation is perpendicular to wafers when the arsenic ions are implanted; photoresist which is located on the surface of the MOS transistor is eliminated; drain source annealing operation is conducted to the MOS transistor and the phosphonium ions extend from the lower portion of the flank to the lower portion of the polysilicon gate to form a N type lightly doped drain region and the arsenic ions form a source region and a drain region. The MOS transistor lightly doped drain region manufacturing method can reduce the processing steps in the MOS transistor lightly doped drain region manufacturing process.

Description

technical field [0001] The invention relates to the technical field of manufacturing semiconductor integrated circuits, in particular to a method for manufacturing a lightly doped drain region of a MOS transistor. Background technique [0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs, usually referred to as MOS transistors), when operating in the saturation region, part of the channel is pinched off, and the carriers flowing through the pinch-off region are accelerated to a very high level by a large electric field. Speed, forming so-called hot carriers; some hot carriers pop out of the channel after colliding with the crystal lattice, some of them enter the substrate to form substrate current, and the other part enters the gate oxide layer; if the MOS transistor continues to work, the hot carrier The carriers will cause its threshold voltage to gradually shift; this is the hot carrier effect of the MOS transistor. [0003] For short-channel transistors, ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/265
Inventor 潘光燃
Owner FOUNDER MICROELECTRONICS INT
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