Package substrate of active chip and preparation method thereof

Abstract

The invention provides a package substrate of an active chip and a preparation method of the package substrate of the active chip. The package substrate of the active chip comprises a core plate. The core plate comprises at least one upper active chip, and at least one lower active chip. The upper active chip is embedded into the core plate, an active face faces toward the lower surface of the core plate, and the upper active chip is an active unpacked chip. The lower active chip is embedded into the core plate, an active face faces toward the upper surface of the core plate and the lower active chip is an active unpacked chip. Due to the fact that the active chips are not packed before being embedded, thinning processing is carried out on the active chips, so that microminiaturization and light weight of the package structure are achieved, and therefore the manufacturing technology of the substrate is simplified. In addition, a plurality of the unpacked chips are simultaneously embedded into two faces of the substrate, and integrality is improved. Meanwhile, the freedom degree and the space on the two faces of the substrate are large, multi-layer wiring can be continuously carried out, and therefore process quality and reliability of electrical connection are improved.

Description

technical field [0001] The invention relates to the technical field of system packaging in the microelectronics industry, in particular to an active chip packaging substrate and a method for preparing the substrate. Background technique [0002] Modern portable electronic products put forward higher requirements for microelectronic packaging. With the continuous pursuit of lighter, thinner, smaller, high reliability and low power consumption, microelectronic packaging is also moving towards higher density and smaller size. Small package form development. Microelectronic packaging will develop from packaging, less packaging to no packaging, so Direct Chip Attach (DCA) technology has attracted more and more attention. Direct chip bonding technology is a packaging technology with the highest packaging efficiency. It directly bonds the chip to the printed circuit board or substrate without packaging. The advantage is that it has better electrical properties and more direct heat...

AI Technical Summary

Problems solved by technology

[0006] U.S. Patent No.7663249B2 proposes a chip packaging structure and manufacturing method, such as Figure 1B As shown, in this method, the packaged chips 108 and 208 are respectively connected to two substrates by flip-chip welding technology, and a layer of dielectric layer 120 is first laminated on a substrate connected to the packaged chip 108, and then another The substrate that has been flip-chip connected to the packaged chip 208 is pressed face down to the dielectric layer 120, and then the substrates on both sides are removed, thus realizing the embedding of multiple packaged chips, but in the above-mentioned patent, the chips are flip-chip connected to the substrate Then press the dielectric layer, so when there are many bumps and the spacing is relatively small, it is possible that the dielectric layer cannot completely fill the gap between the bumps of the chip and the bumps (ie Figure 1B In B), the existence of bubbles is caused, and the chip has been packaged, so the size of the chip itself is very large, and the package structure will be relatively large, so it is difficult to reduce the size of the entire package

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