Field programmable gate array (FPGA)-based superfast auxiliary encoder system (AES) processor and implementing method thereof

A processor, ultra-high-speed technology, applied in the field of communication, can solve problems such as large resource occupation, long delay time, complex control logic, etc., to achieve the effect of ensuring effectiveness, improving reliability, and simple storage control logic

Inactive Publication Date: 2013-06-12
XIDIAN UNIV
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  • Summary
  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The purpose of the present invention is to overcome the deficiencies of the above-mentioned prior art, solve the problems of traditional AES processor control logic complexity, long delay time between input and output, and occupy m

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  • Field programmable gate array (FPGA)-based superfast auxiliary encoder system (AES) processor and implementing method thereof
  • Field programmable gate array (FPGA)-based superfast auxiliary encoder system (AES) processor and implementing method thereof
  • Field programmable gate array (FPGA)-based superfast auxiliary encoder system (AES) processor and implementing method thereof

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Embodiment Construction

[0042] The present invention will be further described below in conjunction with the accompanying drawings.

[0043] Refer to attached figure 1 The overall structure of the processor of the present invention is further described.

[0044] The processor of the present invention includes an interface storage area buffer module, a control module, an AES encryption and decryption module, a read-only memory lookup table module, a register module, and an output module; the interface storage area buffer module and the AES encryption and decryption module are connected through a data bus and a control bus ; The read-only memory look-up table module, the register module, the control module and the output module are connected through the data bus and the control bus.

[0045] The interface storage area buffer module is used for temporarily storing the data on the input data bus. The interface storage area buffer module includes four random access memory RAMs arranged in the front buff...

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Abstract

The invention discloses a field programmable gate array (FPGA)-based superfast auxiliary encoder system (AES) processor and an implementing method thereof. The AES processor comprises an interface storage area buffer module, a control module, an AES encryption and decryption module, a read-only memory lookup table module, a register module and an output module. The implementing method for the processor comprises the following steps: 1, initializing a data table; 2, performing initial setting; 3, receiving data; 4, reading the data; 5, selecting a data processing mode; 6, judging whether the encryption and decryption are finished; and 7, outputting a result. The invention mainly solves the problems that an AES processor is controlled complicatedly and modules have low portability, reliability, safety and processing speed in the prior art; and an improved algorithm and a lookup table-based method are used. The AES processor has all levels of structures which are fixed, is simple in control logic, comprises the modules with high portability, is suitable to be implemented in a singlechip FPGA, and has the characteristics of high speed and high accuracy.

Description

technical field [0001] The invention belongs to the technical field of communication, and further relates to an ultra-high-speed Advanced Encryption Standard (AES) processor based on a Field Programmable Gate Array (Field Programmable Gate Array, FPGA) in the technical field of information security and an implementation method thereof. The invention fully utilizes the flexibility of FPGA programming and the reliability of hardware under the condition of high processing speed and minimum resource occupation, and realizes safe encryption of data and information. The present invention can be widely used in smart cards (smart cards), mobile banking systems, and ATM cash machines for high-level encryption and decryption, so as to ensure the safety of data and information. Background technique [0002] With the development of communication technology, the communication environment is becoming more and more complex. Compared with traditional software encryption methods, hardware en...

Claims

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Application Information

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IPC IPC(8): H04L9/06
Inventor 刘景伟蔡鑫孙蓉李勇白宝明
Owner XIDIAN UNIV
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