Method of making semiconductor device

Abstract

The invention discloses a method for manufacturing a semiconductor device. The method comprises the steps of providing a semiconductor substrate, wherein an interlayer dielectric layer is formed on the semiconductor substrate, and a first filling opening and a second filling opening are formed in the interlayer dielectric layer; sequentially forming first work function layers and first carbon-based material layers on the interlayer dielectric layer and inside the first filling opening and the second filling opening, and implementing a planarization process; forming covering layers on the interlayer dielectric layer, first work function layers and first carbon-based material layers; removing the covering layer on the first filling opening as well as the first work function layer and the first carbon-based material layer inside the first filling opening; sequentially forming second work function layers and second carbon-based material layers inside the first filling opening and on covering layers; implementing the planarization process; removing first carbon-based material layers and second carbon-based material layers to form a first opening and a second opening; and filling the first opening and the second opening with grid material layers to form a N-type metal grid and a P-type metal grid respectively. By the aid of the method, metal grids can be prevented from being damaged by subsequent processes.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for manufacturing a semiconductor device. Background technique [0002] As the gate size shrinks to tens of nanometers, the thickness of the gate oxide layer drops below 3nm, causing problems such as excessive gate resistance, increased gate leakage, and depletion of the polysilicon gate. Therefore, people turn their attention to the metal gate technology again. The metal gate technology uses a metal with a lower resistance as the gate, and a material with a larger dielectric constant as the gate dielectric layer. [0003] The metal gate technology includes a gate-first process and a gate-last process. The Gate-first process refers to the formation of metal gates before performing drain / source region ion implantation and subsequent high-temperature annealing steps on the silicon wafer, while the Gate-last process is the opposite. Since the metal gate in the Gate...

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Problems solved by technology

During these processes, the etching gas and / or cleaning solution can easily damage the P-type metal gate 106, resulting in failure of the entire semiconductor device.

In addition, when forming the P-type metal gate 106, a chemical mechanical polishing process needs to be performed, and when forming an N-type metal gate, the P-type metal gate 106 needs to perform another chemical mechanical polishing process, and two chemical mechanical polishing processes need to be performed. The grinding process is difficult to control the height loss of the P-type metal gate 106

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