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An enhanced flash chip and a chip packaging method

A chip packaging and enhanced technology, applied in multi-program devices, instruments, circuits, etc., can solve the problems of long design cycle, high design cost, and high design complexity, so as to improve yield, avoid cross problems, and reduce process effect of complexity

Active Publication Date: 2016-12-28
GIGADEVICE SEMICON (BEIJING) INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The invention provides an enhanced Flash chip and a chip packaging method to solve the problems of high design complexity, long design cycle and high design cost

Method used

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  • An enhanced flash chip and a chip packaging method
  • An enhanced flash chip and a chip packaging method
  • An enhanced flash chip and a chip packaging method

Examples

Experimental program
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Effect test

Embodiment 1

[0067] Embodiment 1 of the present invention provides an enhanced Flash chip, and the chip may include: FLASH and RPMC packaged together.

[0068] In the embodiment of the present invention, the FLASH and the RPMC may be independent chips. FLASH can choose different capacities to meet the needs of different systems. This FLASH can reuse the designed FLASH chip, so it does not need to be redesigned, which greatly reduces the development cycle; RPMC has the function of response protection monotonic counting, and can also be used alone .

[0069] In the enhanced Flash chip proposed by the embodiment of the present invention, the FLASH and the RPMC may respectively include independent controllers. For commands sent from outside, FLASH and RPMC will control FLASH and RPMC to receive and decode them respectively through their independent controllers, and perform corresponding operations when the decoding is successful.

[0070] In addition, FLASH and RPMC can have the same IO pins...

Embodiment 2

[0082] In the following, the enhanced Flash chip will be introduced in detail through Embodiment 2 of the present invention.

[0083] refer to Figure 1-a , Figure 1-b , which shows a schematic diagram of logical connections of an enhanced Flash chip according to Embodiment 2 of the present invention.

[0084] from Figure 1-a , Figure 1-b It can be seen that the enhanced Flash chip described in the embodiment of the present invention may include FLASH and RPMC packaged together.

[0085] Among them, both FLASH and RPMC include multiple pins respectively, and the same IO pins in RPMC and FLASH can be connected to the same set of external shared pins, and the commands sent externally will be received by RPMC and FLASH at the same time, RPMC and FLASH FLASH can respond accordingly; FLASH and RPMC each also include a first internal IO pin and a second internal IO pin, and FASH and / or RPMC connect the first IO internal pin to the corresponding RPMC and RPMC through the set P...

Embodiment 3

[0157] Next, the specific packaging method of the above chip will be introduced through the third embodiment of the present invention.

[0158] refer to image 3 , which shows a flow chart of a chip packaging method described in Embodiment 3 of the present invention, the packaging method may include:

[0159] Step 300, place the FLASH that needs to be packaged and the response protection monotonic counter RPMC on the chip carrier, the FLASH and the RPMC are independent of each other.

[0160] In the embodiment of the present invention, the FLASH and the RPMC are packaged together to obtain an enhanced Flash chip with RPMC function, and the FLASH and the RPMC in the chip are independent of each other.

[0161] First, the FLASH and RPMC that need to be packaged can be placed on the chip carrier, and the chip carrier described in the embodiment of the present invention can correspond to figure 2 in the Package.

[0162] Preferably, this step 300 may include: placing the FLASH ...

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Abstract

The present invention provides an enhanced Flash chip and a chip packaging method. The Flash chip includes: FLASH packaged together and a response protection monotone counter RPMC; each of the FLASH and the RPMC also includes a first internal IO pin pin and / or the second internal IO pin; the FLASH and / or RPMC is also provided with a jumper window, and one end of the jumper window is interconnected with the first internal IO pin of the FLASH and / or RPMC, The other end of the jumper window is interconnected with the first internal IO pin of the RPMC and / or FLASH; the second internal IO pin of the FLASH is interconnected with the second internal IO pin of the RPMC. The Flash chip provided by the invention effectively reduces design complexity and chip manufacturing cost, and avoids lead wire crossing in chip packaging, thereby improving the yield rate of chip packaging.

Description

technical field [0001] The invention relates to the field of chip technology, in particular to an enhanced Flash chip and a chip packaging method. Background technique [0002] The enhanced Flash with Replay Protection Monotonic Counter (RPMC) is the Basic Input-Output System (BIOS) chip that Intel will promote. It contains a high-capacity Flash chip and RPMC circuit. Among them, the capacity of the FLASH chip can be 8M, 16M, 32M, 64M, 128M, 256M or higher, and is used to store the code and data of the CPU BIOS; the RPMC circuit ensures the confidentiality and integrity of the read and write data. The RPMC circuit and its integrated FLASH constitute the hardware platform of the BIOS in the personal computer (PersonalComputer, PC) system. [0003] At present, when designing a Flash chip with RPMC function, designers usually integrate large-capacity Flash and RPMC on one chip, that is, RPMC circuit and FLASH are designed together. [0004] However, this design method has th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/46H01L25/00H01L23/52
CPCH01L23/57H01L2225/0651H01L2225/06506H01L2225/06568H01L2224/48145H01L2224/48227H01L24/45H01L24/48H01L24/49H01L2224/451H01L2224/4911H01L2224/49171H01L25/0657G11C5/04H01L2224/05554H01L2924/00014H01L25/18H01L25/50H01L2224/43H01L2924/00012G11C16/10G11C16/26H01L24/85H01L23/49838H01L2924/1438
Inventor 胡洪舒清明张赛张建军刘江
Owner GIGADEVICE SEMICON (BEIJING) INC
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