Supercharge Your Innovation With Domain-Expert AI Agents!

Integrated circuit with memory cells comprising addressing bit lines and adjacent bit lines, and operation method

A technology of integrated circuits and memory, applied in the field of memory, can solve the problems of wrong programming adjacent bit read interference effect and so on

Active Publication Date: 2013-09-25
MACRONIX INT CO LTD
View PDF4 Cites 4 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, such an increase in voltage magnitude suffers from the same problem as the read disturb effect which can mistakenly program adjacent bits when the addressed bit is read

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Integrated circuit with memory cells comprising addressing bit lines and adjacent bit lines, and operation method
  • Integrated circuit with memory cells comprising addressing bit lines and adjacent bit lines, and operation method
  • Integrated circuit with memory cells comprising addressing bit lines and adjacent bit lines, and operation method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0049] The example shown here has four possible data values ​​in a memory cell. Other examples could be to have two possible data values, to have eight possible data values, or to have other numbers of possible data values.

[0050] Figure 1 to Figure 2 A schematic diagram of a non-volatile memory cell, which has an address bit and adjacent bits for storing data respectively.

[0051] figure 1 A non-volatile memory cell is shown with data stored in different portions of the silicon nitride storage layer. These different portions of the same memory cell are referred to herein as "addressed bits" and "neighboring bits." In this description, the word "bit" refers to different physical locations in the charge storage layer that can store 1, 2, 3 or more bits of data. The memory cell has a gate terminal, two current carrying terminals - a drain terminal and a source terminal. The drain terminal voltage varies according to the data value near the source terminal. Because the ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses an integrated circuit with memory cells comprising addressing bit lines and adjacent bit lines, and an operation method of the memory cell. A storage layer of a non-volatile memory cell, such as silicon nitride, has two storage parts respectively storing addressable data, and the two storage parts normally are respectively adjacent to a source terminal and a drain terminal. When the data stored in one of the storage part is sensed, an applied drain voltage is based on the data stored in the other storage part. If the data stored in the other storage part is represented by a threshold-voltage exceeding the smallest threshold-voltage, the applied drain voltage is increased. The technology can help to widen a threshold-voltage range in reading operation and programming verification operation.

Description

technical field [0001] The invention relates to the field of memory technology, in particular to an integrated circuit with addressing and adjacent bit memory cells and an operation method of the memory cells. Background technique [0002] Charge trapping memory cells such as silicon nitride read only memory (NROM) can be programmed into different regions of the silicon nitride storage layer by mechanisms such as channel hot electron injection (CHE). A single memory cell can respectively store data of different addresses in different parts of the silicon nitride storage layer near the source and near the drain. The threshold voltage range of a memory cell is associated with the different data values ​​that can be stored in each portion of the memory cell. For example, in each portion of an MLC, four threshold voltage ranges may represent four different data values ​​storing two bits. In a three-level memory cell, eight threshold voltage ranges can represent eight different...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/56G11C16/10
Inventor 陈汉松陈重光洪俊雄
Owner MACRONIX INT CO LTD
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com