Method for exposing through silicon via

Abstract

The invention discloses a method for exposing a through silicon via. The method comprises the steps of firstly forming a through silicon via in a semiconductor substrate, wherein the through silicon via comprises a copper metal layer, a barrier layer and an insulating layer; covering a dielectric layer on the bottom surface of the semiconductor substrate and the through silicon via; forming a sacrificial layer on the dielectric layer; abrading and removing a part of the sacrificial layer, the dielectric layer, the insulating layer and the barrier layer so as to expose the surface of the copper metal layer; etching a part of the insulating layer and the dielectric layer, and forming a concave region around the through silicon via; and finally removing the left sacrificial layer.

Description

technical field [0001] The present invention relates to a method for exposing a through silicon via (TSV). Background technique [0002] Through-silicon via is a conductor structure that runs through the silicon substrate. Its main function is to interconnect integrated circuit chips. Insulation layer, forming a seed layer on the insulation layer, then filling the through hole with metal by electroplating, and then exposing one end of the TSV through crystal back grinding. In this way, the size of the chip can be greatly reduced, the transistor density of the chip can be increased, the performance of electrical interconnection between layers can be improved, the operating speed of the chip can be increased, and the power consumption of the chip can be reduced. [0003] figure 1 and figure 2 One known method of exposing TSVs is illustrated. After the TSV is completed, one end of the TSV 20 will slightly protrude from the bottom surface of the semiconductor substrate 10 o...

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Problems solved by technology

[0004] However, the disadvantage of the above-mentioned backgrinding or CMP process is the shallow dish effect

That is, the surface of the exposed copper metal layer 21 will be slightly sunken inward. In addition, part of the sidewall of the TSV 20 cannot be exposed, so the final TSV structure is not conducive to the three-dimensional When the chip is packaged, the interconnection in the vertical direction is realized

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