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Detection layout structure and detection method

A layout structure, technology to be detected, applied in the direction of semiconductor/solid-state device testing/measurement, electrical components, electric solid-state devices, etc., can solve the problems that it is difficult to reflect the real situation of the structure, and the detection purpose cannot be achieved, so as to reduce production costs and improve The effect of yield

Active Publication Date: 2013-10-23
SEMICON MFG INT (SHANGHAI) CORP
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Problems solved by technology

However, since the metal vias and metal leads of the metal interconnection have a certain size, the distance B between the parallel and staggered patterns in the formed layout structure 10 is greater than 0.9 μm, and the structure between the head and head of the layout structure is detected. The distance A is greater than 1.0 μm and cannot be further reduced, so that it cannot form a structure suitable for the smaller-sized head-to-head relative structure and parallel phase-staggered structure in the metal interconnection to be detected, thus making it difficult for the detection results to reflect the metal to be detected. The real structure of the interconnection line cannot achieve the purpose of detection

Method used

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Embodiment Construction

[0029] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.

[0030] Secondly, the present invention is described in detail by means of schematic diagrams. When describing the examples of the present invention in detail, for the convenience of explanation, the schematic diagrams are not partially enlarged according to the general scale, which should not be used as a limitation of the present invention.

[0031] In this embodiment, the "horizontal", "longitudinal" and "45-degree direction" are relative terms, and in general, the horizontal and vertical directions formed thereof are parallel to the direction of the metal leads f...

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Abstract

The invention provides a detection layout structure and a detection method. The detection layout structure comprises a plurality of transverse graphs, a plurality of longitudinal graphs, through-hole wires lines and contact bonding pads, wherein the transverse graphs are correspondingly connected with the longitudinal graphs through the through-hole lines so as to form a plurality of 45-degree ladder type chains. Each of the ladder type chains excepts for those located at the most peripheral part of the detection layout structure is provided with two adjacent ladder type chains, wherein the transverse graph of one adjacent ladder type chain and a corresponding transverse graph of the current ladder type chain form an opposite structure head to head, and the transverse graph of the other ladder type chain and the corresponding transverse graph of the current ladder type chain form a parallel alternating structure. The detection layout structure and the detection method provided by the invention can detect the connection performance formed by metal leads with small dimensions and the through-hole lines, and improve the performance of semiconductor devices.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a detection layout structure and a detection method. Background technique [0002] Since the advent of semiconductor devices, the integration of semiconductor devices has become higher and higher, and the size of semiconductor elements has been gradually reduced. As semiconductor devices continue to shrink in size and increase in density, one of the limitations is the requirement to form reliable integrated circuit circuits at smaller critical dimensions. For example, after the formation of the conductive interconnection layer of the electronic circuit, it is measured for electrical continuity, so as to determine the reliability of the semiconductor device and the electrical continuity of the integrated circuit circuit. The measurement of electrical continuity, also known as wafer acceptance testing (WAT), is used to quickly determine and correct process variables that may cau...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/544H01L21/66
Inventor 王贵明
Owner SEMICON MFG INT (SHANGHAI) CORP
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