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Data packet processing board and processing method

A processing method and data packet technology, applied in the direction of data exchange network, digital transmission system, electrical components, etc., can solve problems such as uneven load, reduce system computing density, increase NP access memory pressure, etc.

Active Publication Date: 2013-10-23
SUGON INFORMATION IND
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  • Abstract
  • Description
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AI Technical Summary

Problems solved by technology

[0003] The above-mentioned dual NP scheme will have load imbalance between the two NPs. For example, the data traffic received by one NP is 25G, and the processing capacity of the NP has greatly exceeded its processing capacity, while the data traffic received by the other NP is only 5G. The processing capacity of NP is not reasonably utilized, one NP is overloaded, and one NP is not assigned a reasonable workload, and there is obvious uneven load, which seriously limits the processing efficiency of the packet processing board.
If dynamic load balancing processing is added, additional overhead will be generated, and the dual NP solution is difficult to directly access 40G traffic on the board, and additional preprocessing boards or interface boards are required. In the case of limited slots in the chassis, the The computational density of the entire system
In addition, some algorithms will increase the pressure of NP access memory, which is not suitable for NP implementation

Method used

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Embodiment Construction

[0021] Such as figure 1 As shown, the present invention provides a data packet processing board, including: FPGA (Field-Programmable Gate Array) main processing unit, co-processing unit, switching unit, POS (Package over SDH, using SDH backbone) Intermediate protocol layer for network transmission of IP packets) daughter card interface unit, CPB (Control Processing Board, control processing board) interface unit, RTM (Rear Transition Module) interface unit, QDR (Quad Data Rate, 4 times the rate) SRAM), TCAM (Ternary Content Addressable Memory, tri-state content addressable memory) and DDR3, where the FPGA main processing unit is connected to the POS daughter card interface unit, and is connected to the co-processing unit through the Interlaken bus, and through the GE or 10GE bus Connected to the switching unit, the FPGA main processing unit is used to receive data, extract message information, pre-search message information, instruct the co-processing unit to search for detailed...

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Abstract

The invention provides a data packet processing board and a processing method, and is characterized in that an FPGA (Field Programmable Gate Array) is taken as a main processing unit on the data packet processing board so as to be responsible for data acceptance, message information extraction, TCAM (Ternary Content Addressable Memory) pre-search and DPI (Deep Packet Inspection), and an XLP (eXtrem Low Power) chip is taken as an auxiliary processing unit so as to be responsible for specific message information rule search, flow sampling, load balance control and relative system management. According to the invention, advantages of data processing of the FPGA and advantages of an interrupt control of the XLP chip and the system management are combined, so that the problems of the current dual-NP (Network Processor) data packet are effectively solved.

Description

Technical field [0001] The invention relates to a data packet processing board and a processing method. Background technique [0002] At present, the data packet processing board of the dual NP (Network Processor) solution represented by REDSYS can support the data processing speed of 40G traffic. Dual NP scheme, that is, there are two completely independent NPs on one board, each responsible for 20G traffic processing tasks. [0003] The above dual NP scheme will have the load imbalance between the two NPs. For example, the data traffic received by one NP is 25G, the processing capacity of the NP has greatly exceeded its processing capacity, and the data traffic received by the other NP is only 5G. The processing capacity of NP is not used reasonably, one NP is overloaded, and one NP is not allocated a reasonable workload. There is obvious uneven load, which severely limits the processing efficiency of the packet processing board. If you add dynamic load balancing processing, ad...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/24H04L12/803
Inventor 姚文浩柳胜杰张克功袁海滨
Owner SUGON INFORMATION IND
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