Ultralow-power-consumption mixed type content addressable memory

Abstract

The invention discloses an ultralow-power-consumption mixed type content addressable memory. According to the ultralow-power-consumption mixed type content addressable memory, a circuit structure of a word structure control circuit (102') comprises a fourth PMOS (P-channel Metal Oxide Semiconductor) transistor (P4), a fourth NMOS (N-channel Metal Oxide Semiconductor) transistor (N4) and a second NMOS transistor (N2) which are sequentially connected between a positive voltage input end and a negative voltage input end in series; a first matched line (ML1) in a NAND block (101) is electrically connected with the second NMOS transistor (N2) by a phase inverter (F); a second matched line (ML2) in a NOR block (103) is electrically connected with the fourth PMOS transistor (P4), the fourth NMOS transistor (N4) and a third NMOS transistor (N3) respectively; a word structure matched line (ML) is led out between the fourth PMOS transistor (P4) and the fourth NMOS transistor (N4). According to the ultralow-power-consumption mixed type content addressable memory disclosed by the invention, not only can direct-current power consumption be avoided in a pre-charging phase and the pre-charging capability be improved, but also level shake on the word structure matched line ML can be greatly reduced, even eliminated, so that the accuracy of an output result of the word structure matched line ML is ensured.

Description

technical field [0001] The present invention relates to the field of storage technology, in particular to an ultra-low power consumption hybrid content addressable memory (Content Addressable Memory in English, abbreviated as CAM). Background technique [0002] In modern SoC (System on Chip, system on chip), the speed difference between the on-chip high-speed microprocessor and the main memory is the main bottleneck restricting the system performance, and the cache memory is an effective means to solve this problem. In the cache memory, the comparison speed of the address comparator and the power consumption caused by the comparison will directly affect the overall performance of the SoC. Since CAMs with parallel comparison capability can obtain very fast comparison speeds, CAMs are widely used as comparators for cache memories; however, since CAMs generate a large amount of power consumption during operation, how to implement low-power CAMs become a research hotspot in thi...

AI Technical Summary

Problems solved by technology

[0007] (1) In the NAND block 101, if the comparison result of the NAND block 101 is a match during the previous match, then the first match line ML1 is at a low level, and the output of the inverter F is at a high level, The second NMOS (Negative channel Mental Oxide Semiconductor, N-type metal oxide semiconductor) transistor N2 and the third NMOS transistor N3 are both turned on, so the inverter F and the second NMOS transistor N2 form a half-latch structure, and the inverter F The latch is at a high level, and the second NMOS transistor N2 is latched to be turned on; when the previous match ends and enters the pre-charge stage of this match, the first PMOS (Positive channel Metal Oxide Semiconductor, P-type metal oxide semiconductor ) transistor P1 is turned on, and the first PMOS transistor P1 and the second NMOS transistor N2 form a DC path, thus causing DC power consumption; if the size of the first PMOS transistor P1 and the second NMOS transistor N2 are not set properly at this time, then It is very likely that the inverter F cannot be reversed, and the first matching line ML1 may not be precharged to a qualified high level, thereby affecting the normal operation of the CAM

[0008] (2) In the case where the comparison result of the NAND block 101 is a match, and the comparison result of the NOR block 103 is a mismatch, when the discharge amount of the first match line ML1 fails to cause the inverter F to reverse, The second matching line ML2 has not yet started to discharge, the fourth NMOS transistor N4 is still turned on, and the word structure matching line ML will be discharged through the first discharge circuit T1; when the second matching line ML2 starts to discharge, but its discharge capacity does not reach N4 When the threshold is set, the word structure matching line ML will discharge simultaneously through the first discharge circuit T1 and the third discharge circuit T3; this will cause level jitter on the word structure matching line ML, which may cause the word structure matching line ML to output wrong result

[0009] (3) In the case where the comparison result of the NOR block 101 is a match, and the comparison result of the NOR block 103 is a mismatch, the second match line ML2 will be discharged to zero, which will consume a large amount of power consumption

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