Electrostatic Discharge Clamp Circuit with Bias Circuit in 90nm CMOS Technology

Abstract

The invention discloses a static discharge clamping circuit with a bias circuit in a 90 nanometer CMOS (complementary metal-oxide-semiconductor transistor) process. The static discharge clamping circuit mainly solves the problem of great RC (resistance-capacitance) network static electricity leakage in the static discharge clamping circuit in the existing 90 nanometer CMOS process. The circuit comprises an RC network, a phase inverter, a clamping device and a bias circuit, wherein the bias circuit provides bias voltage Vb of a grid electrode for a PMOS (P-channel metal oxide semiconductor) tube Mp3 in the RC network, as the bias voltage Vb is high voltage, the source grid voltage of the PMOS tube Mp3 is reduced, the equivalent resistance is increased, and the static electricity leakage of the RC network is reduced; during the static discharge, after the bias RC network detects the static discharge, the detection voltage CLK is input into the phase inverter, after the phase inverter receives the detection voltage, the grid electrode driving voltage Vg is input into the clamping device for starting the clamping device, and the static discharge charges are discharged. The static discharge clamping circuit has the advantages that the energy efficiency of the static discharge clamping circuit in the 90 nanometer CMOS process is improved, and the static discharge clamping circuit can be used for the design of integrated circuits.

Description

technical field

[0001] The invention belongs to the technical field of electronic circuits and relates to electrostatic discharge protection, in particular to an electrostatic discharge clamping circuit with a bias circuit in a 90nm CMOS process, which can be used in integrated circuit design. Background technique

[0002] During the manufacturing, packaging, transportation and use of integrated circuits, various forms of electrostatic discharge events are likely to occur. ESD events are characterized by instantaneous large stress and are one of the main failure modes of integrated circuits. ESD events cannot be completely avoided, so ESD protection must be considered when designing and manufacturing integrated circuits. The intensity of an electrostatic discharge event can be equivalent to a voltage. For example, in the human body model, the equivalent voltage of an electrostatic discharge event where electric sparks can be seen is generally as high as 3kV or more. The an...

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