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Non-capacitive low-dropout linear voltage regulator

A low-dropout linear, capacitor-free technology, applied in the direction of instruments, electrical variable adjustment, control/regulation systems, etc., can solve problems such as poor transient response, improve transient response and system stability, swing The effect of rate enhancement

Active Publication Date: 2014-12-31
SHENZHEN CHIP OPTECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In recent years, many capless LDO solutions have emerged, but the transient response of most solutions is not very good

Method used

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Embodiment Construction

[0019] Vref in the drawings of the manual is the reference voltage source, VDD is the power supply voltage, Mp is the adjustment tube, C1 is the compensation capacitor, Va and Vb are the bias voltage, MA 1 For the first PMOS transistor, MA 2 For the second PMOS transistor, MA 3 For the third PMOS transistor, MA 4 For the fourth PMOS transistor, MA 5 For the first NMOS tube, MA 6 For the second NMOS transistor, MA 7 For the third NMOS transistor, MA 8 For the fourth NMOS transistor, MA 9 For the fifth NMOS tube, MB 1 For the fifth PMOS transistor, MB 2 For the sixth PMOS transistor, MB 3 For the seventh PMOS transistor, MB 4 For the sixth NMOS tube, MB 5 For the seventh NMOS tube, MB 6 For the eighth NMOS tube, MB 7 is the ninth NMOS transistor, R1 is the first resistor, R2 is the second resistor, RL is the load, and CL is the on-chip load capacitance.

[0020] Such as Figures 2 to 6 As shown, the system block diagram of a non-capacitor low dropout linear regulat...

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Abstract

The invention relates to a non-capacitive low-dropout linear voltage regulator. The non-capacitive low-dropout linear voltage regulator comprises a reference voltage source, an error amplifier, a supply voltage input end, a regulating pipe, a resistance feedback circuit, a slew rate enhancement circuit and a compensation capacitor, wherein a non-inverting input end of the error amplifier is connected with the resistance feedback circuit, an inverting input end of the error amplifier is connected with the reference voltage source, an output end of the error amplifier is connected with an input end of the slew rate enhancement circuit, an output end of the slew rate enhancement circuit is connected with a grid electrode of the regulating pipe, a drain electrode of the regulating pipe serves as an output end, the drain electrode of the regulating pipe is connected with the resistance feedback circuit, a source electrode of the regulating pipe is connected with the supply voltage input end, one end of the compensation capacitor (C1) is connected with the grid electrode of the regulating pipe, and the other end of the compensation capacitor (C1) is connected with the output end of the regulating pipe.

Description

technical field [0001] The invention relates to a voltage regulator, in particular to a low-dropout linear voltage regulator without capacitance. Background technique [0002] LDO (low dropout regulator) low-dropout linear regulator is an important circuit in the field of power management. It has the advantages of small size, few peripheral components, simple structure, low output noise, low cost, and low power consumption. It is widely used used in electronic systems. [0003] Such as figure 1 As shown, a typical LDO circuit is generally composed of a reference voltage source Vref, an error amplifier, a power supply voltage input terminal VDD, a regulator transistor Mp, and a resistor feedback circuit. The non-inverting input terminal of the error amplifier is connected to the resistor feedback circuit, and the inverting input terminal is connected to the reference The voltage source Vref is connected, the output terminal is connected to the gate of the adjustment tube Mp...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G05F1/56
Inventor 吴小刚
Owner SHENZHEN CHIP OPTECH