The inventive idea of the present invention is:
 According to the CCD imaging unit may output low-speed, medium-speed and high-speed image data, the corresponding transmission system is designed, and the ECC error correction coding strategy is adopted during transmission, which improves the transmission reliability. The image real-time compression unit adopts the dedicated compression chip ADV212. According to the working characteristics of ADV212 and the characteristics of multi-channel CCD image output, Custom working mode and frame construction strategy are adopted to realize the single-chip ADV212 processing multi-channel CCD image data. The compressed code stream is stored in a large-capacity NAND flash memory. In order to prevent the single event flipping phenomenon in the memory, the RS error correction algorithm is used in this article. Finally, the compressed code stream adopts the G-level transmission scheme, which greatly reduces the transmission channel. The whole device uses FPGA as the main processor, which can seamlessly connect with other camera systems.
 The spatial TDICCD camera image real-time transmission, compression and storage device of the present invention includes:
 The high, medium and low speed transmission unit of each channel of CCD is used to transmit the image data output by each channel of CCD imaging unit. According to the different clock frequency of pixel transfer in each channel, it is designed as a low-speed, medium-speed and high-speed transmission system. Low-speed transmission system uses LVDS transmission (parallel clock frequency is less than 55MHz), medium speed uses Camera Link protocol transmission (parallel clock frequency is less than 80MHz), and high-speed uses G bit transmission (parallel clock frequency is greater than 80MHz). In order to improve the transmission reliability, the VLSI structure of the ECC algorithm for FEC error correction is designed, that is, ECC is used for encoding before transmission, and ECC is decoded during reception. Because the ECC algorithm uses FPGA to achieve almost no impact on the transmission speed, it is very suitable for CCD image data transmission.
 The image frame construction unit is used to construct the image frame required by the compression chip. Usually the number of CCD output channels is as high as dozens. If each channel is compressed by a compression unit, it will inevitably take up a lot of resources. Therefore, the present invention uses the image frame construction unit to compress the multi-channel image in a pipeline manner, and only one compression unit can process the multi-channel data.
 The compression parameter memory is used to store the coding parameters for the normal operation of the compression chip. The invention adopts the RAM moving strategy, the compression parameters are moved to the RAM when the system is powered on, and then imported from the RAM to the compression chip when the compression is in progress. Since the rate of importing from RAM to compression chip is much faster than importing from external memory to compression chip, this strategy greatly improves the configuration efficiency of compression chip.
 The compression chip controller is used to control the normal operation of the compression chip, set its encoding parameters, memory, handle interrupt events, and receive data from the image frame construction unit. The whole design adopts FPGA programming to realize seamless connection with other camera systems.
 The compression chip array is used to compress images. The compression chip adopts ADV212. The chip adopts the world's most advanced processing technology and the JPEG2000 compression algorithm. It is very convenient to control, and the compression performance is higher than the commonly used compression algorithms. The maximum compression rate reaches 1M sample/s, which can meet the real-time compression applications of various CCD cameras.
 The storage array controller and error correction encoder are used to control the large-capacity storage array to store image data in real time, control the operations of solid storage erasure, read and write, and bad block management. At the same time, the pipeline strategy is used to store multi-channel CCD image data. In order to prevent the memory from flipping due to single event flipping and causing image data errors. The invention designs an error correction strategy based on the RS code, performs encoding before storage, and performs error detection and correction after reading, thereby improving the reliability of image data storage.
 Large-capacity solid storage unit, used to store compressed code streams. Large-capacity solid storage uses NAND flash memory. NAND flash memory has high-speed access, small size, low power consumption, light weight, shock resistance, impact resistance, wide temperature adaptation range, non-volatile, and large capacity, which is very suitable for space camera applications.
 The compressed code stream transmission unit is used to transmit the image compression code stream to the satellite data transmission system. The present invention adopts a high-speed G-level transmission strategy, and can transmit each channel CCD image compression code stream with fewer transmission channels, which can reduce the complexity of the transmission system. In addition, RS coding error correction strategy is adopted before transmission to ensure transmission reliability.
 Hereinafter, the present invention will be further described in detail with specific embodiments in combination with the drawings.
 figure 1 A specific implementation of the spatial TDICCD camera image real-time transmission, compression and storage device of the present invention is shown. See figure 1 , Which includes: CCD channel high, medium and low speed transmission unit 1, image frame construction unit 2, compression parameter memory 3, compression chip controller 4, compression chip array 5, storage array controller and error correction encoder 6, large-capacity solid storage Unit 7, compression code stream transmission unit 8.
 The high-, medium-, and low-speed transmission unit 1 of each channel of the CCD, which is connected to the camera CCD imaging unit, includes: a low-speed transmission unit, a medium-speed transmission unit, a high-speed transmission unit, and an error correction ECC encoding module. Each transmission unit includes a transmission protocol and a read-write control unit.
 The image frame construction unit 2 includes: an SDRAM including an SDRAM initialization state machine, a refresh operation state machine, a data read state machine, a data write state machine, and a ping-pong operation SDRAM. Used to construct an image frame with a size of M×N.
 The compression parameter memory 3 includes: EEROM memory, I2C protocol read-write control unit and RAM. Used to import the compression coding parameters to the compression chip to work normally.
 The compression chip controller 4 includes: ADV212 encoding parameters, a memory setting state machine, an image data input unit, an image buffer, a compressed code stream reading unit, etc.
 The compressed chip array 5 includes: ADV212, chip configuration circuit and crystal oscillator. Used to compress multi-channel CCD image data.
 The storage array controller and the error correction encoder 6 include: a flash memory read state machine, a write state machine, an erase state machine, a bad block management unit, and an RS error correction encoding unit.
 The large-capacity solid storage unit 7 includes: a NAND flash memory array and a power supply unit.
 The compressed code stream transmission unit 8, which is connected to the satellite transmission interface, includes: G-level transmission chip, transmission protocol, data transmission link establishment and error correction coding unit.
 Obviously, the foregoing embodiments are merely examples for clear description, and are not intended to limit the implementation. For those of ordinary skill in the art, other changes or changes in different forms can be made on the basis of the above description. There is no need and cannot give an exhaustive list of all implementation methods. The obvious changes or changes derived from this are still within the protection scope of the present invention.