An Apparatus for Verifying Advanced Microcontroller Bus Interfaces

Abstract

The invention discloses a device for verifying the bus interface of an advanced micro-controller, comprising: a parameter generating unit, which is used to generate a random transmission packet according to constraint conditions, and the transmission packet includes parameters such as data, address, read-write type, burst length, etc. ; The transmission unit is used to randomly transmit the content of the packet to generate different commands; the drive unit is used to convert different commands into signals on the interface and send them to the verification object; the detection unit is used to monitor the behavior of the verification object bus, And check the correctness of the protocol of the bus in real time; the function coverage statistics unit is used to receive the transmission packet sent by the transmission unit and / or the detection unit, and perform the coverage statistics of the bus behavior according to its content, including access type, address space At least one of , data space, and burst type. The device provided by the invention is applicable to any system-level or module-level verification based on the advanced micro-controller bus architecture AMBA, and can improve the design verification efficiency of the whole chip.

Description

technical field [0001] The invention relates to the technical field of system chips, in particular to the verification technology of system chips. The present invention relates to a device for verifying the bus interface of an advanced microcontroller. Background technique [0002] As leading system-on-chip (SoC, System on Chip) designs include more complex protocols, the intellectual property (VIP, Verification Intellectual Property) used for verification has become an important part of the verification environment and enables Engineers were able to meet coverage targets on tight project schedules. VIP provides various on-chip and off-chip functional models such as PCI Express, USB, MIPI, HDMI, Ethernet, etc. Verification engineers use these models to test all SoC interfaces prior to tapeout, enabling them to verify that an interface complies with published standards. [0003] The SystemVerilog Verification Methodology (VMM) introduced by electronic design automation (...

AI Technical Summary

Problems solved by technology

For the standards before AMBA3.0, there are related commercial VIPs, but most of them are based on related verification methodologies (or simulation work), and there is no VIP based solely on System Verilog language

[0007] In response to the need for higher performance and power efficiency, the industry is now seeing widespread and rapid adoption of the AMBA4AXI4 TM and ACE TM Protocol to support sustainable, diverse and multi-processor SoC chips. After the introduction of the AMBA 4.0 standard, there is no mature VIP to verify the bus interface of AXI4 and ACE. Therefore, it is necessary to develop a set of AMBA VIP, which is compatible with AMBA4 All standards below .0 have nothing to do with verification methodology or simulation tools. Based on the system verilog language, they can be integrated into any SoC verification environment of the AMBA system

Images