Display device, array substrate and manufacturing method of array substrate

A technology of an array substrate and a manufacturing method, applied in the field of display devices, can solve the problems of easy disconnection, large resistance value of source-drain electrode lines, etc.

Active Publication Date: 2013-12-25
HEFEI BOE OPTOELECTRONICS TECH +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The technical problem to be solved by the present invention is to provide a display device, an array substrate and a manufacturing method thereof, so as to overcome the defects in the prior art that the resistance value of the source-drain electrode line is relatively large and is prone to disconnection

Method used

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  • Display device, array substrate and manufacturing method of array substrate
  • Display device, array substrate and manufacturing method of array substrate
  • Display device, array substrate and manufacturing method of array substrate

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Embodiment 1

[0033] In this embodiment, an array substrate is provided, and the array substrate is described by taking a bottom gate structure as an example.

[0034] Such as figure 1 and Figure 6 As shown, the array substrate includes a substrate 0, on which a gate 11, a gate insulating layer 21, an oxide active layer, an etching stopper layer 23, a source-drain electrode layer 31, a passivation layer 41 and a pixel The electrode layer 51 ; the passivation layer 41 is provided with a via hole 42 , and the pixel electrode layer 51 is connected to the drain electrode through the via hole 42 .

[0035] The oxide active layer includes a non-metallized semiconductor region 22 and a metallized metal oxide conductor region 24;

[0036] The semiconductor region 22 corresponds to the position of the etching stopper layer 23;

[0037] The metal oxide conductor region 24 corresponds to the position of the source-drain electrode 31 and is located below the source-drain electrode 31 .

[0038] Wh...

Embodiment 2

[0041] An embodiment of the present invention provides an array substrate, which is different from Embodiment 1 in that the array substrate in this embodiment has a top-gate structure.

[0042] The array substrate may include a substrate on which a pixel electrode layer, a source-drain electrode layer, an oxide active layer, a barrier layer, a gate insulating layer and a gate are arranged, wherein the pixel electrode layer is connected to the drain electrode.

[0043] Wherein, the oxide active layer includes a semiconductor region that has not been metallized and a metal oxide conductor region that has been metallized;

[0044] The semiconductor region corresponds to the position of the etching barrier layer;

[0045] The metal oxide conductor region corresponds to the position of the source-drain electrode layer and is located above the source-drain electrode layer.

[0046] Wherein, the oxide active layer includes at least one of InGaZnO, InGaO, ITZO, and AlZnO. Of course,...

Embodiment 3

[0049] Such as Figure 7 As shown, based on the array substrate structure of Embodiment 1, the present invention also provides a method for manufacturing an array substrate, which specifically includes:

[0050] Forming the pattern of the gate on the substrate;

[0051] Specifically, refer to figure 2 , deposit a gate metal film on the substrate 0, and form the pattern of the gate 11 through a patterning process. The patterning process specifically includes processes such as exposure, development, etching and stripping, and can also be a printing or screen printing process.

[0052] patterning the gate insulating layer, the oxide active layer and the etch stop layer;

[0053] Specifically, refer to image 3 1. Deposit gate insulating material, oxide semiconductor material 22 and etch stop layer material on the substrate after step 1, and form patterns of gate insulating layer 21, oxide semiconductor material and etch stop layer 23 through a patterning process.

[0054] Wh...

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Abstract

The invention relates to the technical field of display, in particular to a display device, an array substrate and a manufacturing method of the array substrate. The array substrate comprises an oxide active layer. The oxide active layer comprises a semiconductor area which does not undergo metallization processing and a metal oxide conductor area which undergoes metallization processing. According to the embodiment of the display device, the array substrate and the manufacturing method of the substrate, by performing metallization processing on partial area in the oxide active layer, a metal oxide conductor layer is formed. Due to the fact that the metal oxide conductor layer has conductor characteristics, the resistance of a drain and source electrode layer can be effectively reduced, and the probability of line breaking of the drain and source electrode layer is reduced to the maximum.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to a display device, an array substrate and a manufacturing method thereof. Background technique [0002] Liquid crystal display, as an important flat panel display method, has developed rapidly in the past ten years. Liquid crystal displays have the advantages of lightness, thinness, and low energy consumption, and are widely used in modern information equipment such as televisions, computers, mobile phones, and digital cameras. In recent years, oxide thin film transistors (Oxide TFTs) have attracted the attention of the industry due to their high mobility. Oxide can reduce the size of thin film transistors and improve resolution due to its higher mobility. In order to increase the resolution, the width of the source-drain electrode lines needs to be reduced, but this will cause the metal lines to be prone to disconnection. Contents of the invention [0003] (1) Techn...

Claims

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Application Information

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IPC IPC(8): H01L27/12H01L21/77G02F1/136G02F1/1333
CPCG02F1/136286H01L29/7869H01L29/66969H01L29/78618G02F1/136295H01L27/1225H01L27/1244H01L27/127H01L27/1288
Inventor 王盛
Owner HEFEI BOE OPTOELECTRONICS TECH
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