Encapsulation method for chip fan-out encapsulation structure

Abstract

The invention relates to an encapsulation method for a chip fan-out encapsulation structure. The encapsulation method includes the following steps that S1, a chip assembly is provided and comprises a chip and a plastic package shell encapsulated on the chip, the chip comprises a first surface, a second surface and an electrode bonding pad, the first surface and the second surface are oppositely arranged, the electrode bonding pad is exposed outwards from the second surface, the plastic package shell at least encapsulates the first surface, and the electrode bonding pad is not encapsulated by the plastic package shell; S3, a substrate ink line is formed and provided with an electrical connecting end connected with the electrode bonding pad; S4, a first thin film dielectric layer is formed, covers the substrate ink line and is provided with a first opening part enabling the substrate ink line to be partially exposed. Ink leading is adopted in the encapsulation method, so chip encapsulation is achieved. Compared with the prior art, the encapsulation method has the advantages of being simple in process, low in manufacturing cost and short in production cycle and protecting the environment, and meanwhile the problem of current leakage can be solved.

Description

technical field [0001] The invention relates to the field of semiconductor packaging, in particular to a packaging method for a chip fan-out packaging structure. Background technique [0002] The miniaturization, multi-functionalization and rapid replacement of electronic products have put forward requirements for light, thin, short, small, low-cost and flexible IC packaging, which has greatly promoted the development of advanced packaging technology. Therefore, the packaging technology for small chips, narrow-pitch multi-pin and adaptable to various packaging situations is a hot spot in the current packaging field and a future development trend. The chip fan-out packaging structure is to enlarge and arrange the narrow-pitch pins on the small chip by rewiring. This packaging structure can greatly reduce the chip size. Since chips of different designs can share the same substrate and lead frame through rewiring, more pins can be arranged as the package area increases. The e...

AI Technical Summary

Problems solved by technology

These processes are complicated, there are many processes, and corresponding supporting fixtures are required, so the preparation period is long

[0007] 2. Waste of materials, high pollution

[0008] The development and etching process needs to remove the excess thin film dielectric layer and conductive material, resulting in a lot of material waste; a large number of chemical reagents are used in the development, electroplating or chemical crossing and corrosion processes, causing environmental pollution

[0009] 3. Leakage current problem

[0010] The metal on the thin film dielectric layer is difficult to corrode, and it is easy to cause metal residue and leakage current problem

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