Method for removing layers in chip failure analysis process
A failure analysis and chip technology, applied in the field of integrated circuit manufacturing, can solve problems such as low accuracy, inability to continue, and difficulty in analysis, and achieve the effect of ensuring accuracy, good layer removal effect, and small damage.
Active Publication Date: 2014-01-08
SHANGHAI HUALI MICROELECTRONICS CORP
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Problems solved by technology
[0010] However, although nanoscale layer exfoliation can be achieved by using the focused ion beam removal method, there are still certain problems in terms of accuracy.
Those skilled in the art know that the layer removal effect will be the basis of subsequent analysis, and the accuracy is not high, and subsequent analysis will encounter great difficulties, and even cannot continue
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[0029] Attached below Figures 1 to 6 , the specific embodiment of the present invention will be further described in detail. It should be noted that, in order to meet the needs of subsequent detection methods, for example: in the prior art, some methods must be exposed to the surface of the preset target layer, and some methods allow other layers to be placed on the preset target layer, The method for removing layers in the failure analysis process of integrated circuit chips in the embodiment of the present invention can be used to expose features such as figure 1 Any one or more preset target layers of the shown multi-layer integrated circuit chip, these target layers contain target samples to be detected.
[0030] The preset target layer is a gate oxide layer, CT or metal layer, etc. In this embodiment, only the target layer is set as a gate oxide layer, and the gate oxide layer includes a target sample as an embodiment. For the present invention The method of layer remo...
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The invention relates to a method for removing layers in an integrated circuit chip failure analysis process. The method for removing the layers in the integrated circuit chip failure analysis process is applied to at least one preset target layer of an integrated circuit chip of a multi-layer structure, wherein the target layer contains a target sample to be detected. The method for removing the layers in the integrated circuit chip failure analysis process comprises the following steps: selecting one cross section of an integrated circuit chip as a cross section to be ground by adopting a cross section grinding manner, and grinding the cross section to be ground into a final stop cross section; placing a chip sample with the ground cross section into a technological cavity of a focused ion beam device to ensure that the ground cross section is arranged opposite to the transmitting direction of the focused ion beam, so that the preset target layer is parallel to the transmitting direction of the focused ion beam; removing layers above the preset target layer from the surface layer of the integrated circuit chip by adopting the focused ion beam; selectively staying on the surface of the preset target layer by virtue of detection on an electron beam in the focused ion beam. Therefore, the method for removing the layers in the integrated circuit chip failure analysis process has a good layer removing effect.
Description
technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to a method for quickly, accurately and low-damage layer removal in the analysis process of integrated circuit chips. Background technique [0002] Since the advent of semiconductor integrated circuits as a new generation of electronic devices, they have developed extremely rapidly. In the past 20 years, it has experienced three stages of development: small-scale, medium-scale and large-scale integration. At present, it is developing towards the stage of ultra-large-scale integration, and its development and application have become one of the most active and important fields in modern science and technology. [0003] Semiconductor integrated circuit chips go through a lot of complex processes, stacking polysilicon, silicon oxide, metal interconnection layers, etc., so that countless devices are connected together to achieve complex functions. see figure 1...
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IPC IPC(8): G01N1/28
Inventor 陈强
Owner SHANGHAI HUALI MICROELECTRONICS CORP