Chip structure and manufacturing method thereof

A technology of chip structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., and can solve the problems of large chip terminal width, low terminal utilization rate, and limited chip withstand voltage capability.

Active Publication Date: 2014-01-15
BYD SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The purpose of the present invention is to at least solve one of the above-mentioned technical defects, especially the defects of the existing field-limiting r

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  • Chip structure and manufacturing method thereof
  • Chip structure and manufacturing method thereof
  • Chip structure and manufacturing method thereof

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Embodiment Construction

[0033] The embodiments of the present invention are described in detail below. Examples of the embodiments are shown in the accompanying drawings, in which the same or similar reference numerals indicate the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary, and are only used to explain the present invention, and cannot be construed as limiting the present invention.

[0034] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", " The orientation or positional relationship indicated by "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying The description does not indicate or i...

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Abstract

The invention provides a chip structure and a manufacturing method thereof. The chip structure comprises a substrate, an active region formed at the active region in the substrate, and a terminal region formed in the substrate, wherein the active region includes a logic circuit of the chip. Besides, the terminal region includes a main node encircling the active region, a plurality of filed limiting rings successively and concentrically encircling the main node, and a plurality of grooves; insulated layers are formed at the inner walls of the grooves; conductive layers are formed on the insulated layers in the grooves; and preset angles are formed between the grooves and the field limiting rings. Because the grooves with the conductive layers are arranged in the terminal region, an objective of improvement of the voltage-withstanding capability of the chip terminal can be achieved. According to the chip structure provided by the embodiment of the invention, the terminal width can be effectively reduced, the chip area and the chip cost are reduced; and the stability of the device can be substantially enhanced.

Description

Technical field [0001] The present invention relates to the field of semiconductor design and manufacturing, in particular to a chip structure and a manufacturing method thereof. Background technique [0002] With the development of semiconductor technology, semiconductor power devices have a trend toward large current and high voltage. However, as the working voltage of the device increases, the requirements for the withstand voltage of the chip terminal are getting higher and higher. In the prior art, the chip size is required to be large enough. Because after the reverse bias voltage is applied to the chip, the doped area in the active area will gradually widen the electric field and add the potential difference to the depletion area, thereby protecting the chip. The expanded electric field approximates a planar junction, so that the active area can easily achieve a higher breakdown voltage. However, since the dicing track and the back of the chip are both at the high potent...

Claims

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Application Information

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IPC IPC(8): H01L29/06H01L29/78H01L21/336
CPCH01L29/401H01L29/407H01L29/66348H01L29/7397
Inventor 刘鹏飞吴海平
Owner BYD SEMICON CO LTD
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