Chip structure and manufacturing method thereof

Abstract

The invention provides a chip structure and a manufacturing method thereof. The chip structure comprises a substrate, an active region formed at the active region in the substrate, and a terminal region formed in the substrate, wherein the active region includes a logic circuit of the chip. Besides, the terminal region includes a main node encircling the active region, a plurality of filed limiting rings successively and concentrically encircling the main node, and a plurality of grooves; insulated layers are formed at the inner walls of the grooves; conductive layers are formed on the insulated layers in the grooves; and preset angles are formed between the grooves and the field limiting rings. Because the grooves with the conductive layers are arranged in the terminal region, an objective of improvement of the voltage-withstanding capability of the chip terminal can be achieved. According to the chip structure provided by the embodiment of the invention, the terminal width can be effectively reduced, the chip area and the chip cost are reduced; and the stability of the device can be substantially enhanced.

Description

Technical field [0001] The present invention relates to the field of semiconductor design and manufacturing, in particular to a chip structure and a manufacturing method thereof. Background technique [0002] With the development of semiconductor technology, semiconductor power devices have a trend toward large current and high voltage. However, as the working voltage of the device increases, the requirements for the withstand voltage of the chip terminal are getting higher and higher. In the prior art, the chip size is required to be large enough. Because after the reverse bias voltage is applied to the chip, the doped area in the active area will gradually widen the electric field and add the potential difference to the depletion area, thereby protecting the chip. The expanded electric field approximates a planar junction, so that the active area can easily achieve a higher breakdown voltage. However, since the dicing track and the back of the chip are both at the high potent...

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to at least solve one of the above-mentioned technical defects, especially the defects of the existing field-limiting ring structure that the chip terminal width is too large, the terminal utilization rate is not high, the chip area is wasted, and the chip withstand voltage is limited.

Images