A flash memory unit and its manufacturing method

Abstract

The invention discloses a flash memory unit, comprising a semiconductor substrate; a gate oxide layer is arranged on the upper surface of the semiconductor substrate, a lower polysilicon gate is arranged on the upper surface of the gate oxide layer, and a dielectric layer is arranged on the upper surface of the lower polysilicon gate, The upper surface of the dielectric layer is provided with an upper polysilicon gate layer; the upper surface of the upper polysilicon gate layer, and one side of the upper polysilicon gate layer, the dielectric layer and the lower polysilicon gate are all provided with an oxide layer; the upper polysilicon gate layer, the dielectric A polysilicon layer is arranged on the electrical layer and the oxide layer on the side of the lower polysilicon gate. The invention also discloses a method for manufacturing the flash memory unit. The flash memory unit of the present invention only includes 1.5 transistors, and the distance between the source and the control gate is small, so its area is small, which overcomes the technical defect of the large area of ​​the traditional flash memory unit, so it can be used widely Applied in the field of semiconductor technology.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a flash memory unit and a manufacturing method thereof. Background technique [0002] Embedded-Flash technology is to embed flash memory circuits into standard logic or hybrid circuit technology. Due to the advantages of efficient integration, it has been widely used in various electronic products and wired communication equipment. A flash memory unit (Flash Cell) constituting a memory circuit is usually a two-layer polysilicon structure. [0003] Such as figure 1 As shown, the specific structure of the traditional flash memory unit is: a semiconductor substrate ( figure 1 The upper surface of the gate oxide layer is provided with a gate oxide layer, and the upper surface of the gate oxide layer is provided with a spaced apart lower polysilicon gate layer ( figure 1 Shown as P0), the upper surface of the lower polysilicon gate layer is provided with a dielectric layer (...

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Problems solved by technology

However, from figure 1 It can be clearly seen that the distance between the source (Source Gate, SG) and the control gate (Control Gate, control gate) is relatively large, and the traditional flash memory unit includes two transistors, so the area of ​​the flash memory unit is relatively large , can not meet people's demand for smaller size of semiconductor components

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