Clock synchronization method and system of power distribution terminal
A power distribution terminal and clock synchronization technology, applied in the field of electric power, can solve problems such as low precision
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Embodiment 1
[0020] figure 1 The implementation process of the clock synchronization method for power distribution terminals provided in this embodiment is shown. For the convenience of description, only the parts related to the embodiment of the present invention are shown. The implementation process is described in detail as follows:
[0021] S11. When the main clock device sends the first message to the power distribution terminal, the power distribution terminal receives the first hardware time stamp and acquires the second hardware time stamp when receiving the first message, and the first hardware time stamp is the hardware time stamp when the master clock device obtains and sends the first message, and when the power distribution terminal sends the third message to the master clock device, the power distribution terminal obtains and sends the The third hardware time stamp when the third message is described and the fourth hardware time stamp is received, and the fourth hardware time...
Embodiment 2
[0055] figure 2 The system architecture of the clock synchronization system of the first power distribution terminal provided by the second embodiment of the present invention is shown, and for the convenience of description, only the parts related to the embodiment of the present invention are shown. It should be noted that the clock synchronization system for power distribution terminals provided in Embodiment 2 and the clock synchronization method for power distribution terminals provided in Embodiment 1 are applicable to each other.
[0056] A clock synchronization system for a power distribution terminal, the clock synchronization system for a power distribution terminal comprising:
[0057] master clock device 1, and one or more power distribution terminals 2;
[0058] The power distribution terminal 2, when the master clock device 1 sends a first message to the power distribution terminal 2, receives a first hardware time stamp and obtains a second hardware time stamp...
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