IO channel debugging method and system between fpga chips

Abstract

The invention provides a method and system for input-output (IO) channel debugging of field programmable gate array (FPGA) chips. The method comprises the steps of enabling a main control FPGA chip and an auxiliary control FPGA chip to respectively send first training sequences for signal sampling training to each other; enabling the main control FPGA chip to send a second training sequence to the auxiliary control FPGA chip after finishing signal sampling training; enabling the auxiliary control FPGA chip receiving the second training sequence to also send the second training sequence to the main control FPGA chip after finishing the signal sampling training and simultaneously enter a normal communication mode; and enabling the main control FPGA chip receiving the second training sequence to also enter a normal communication mode. By using a main control unit, an auxiliary control unit and the two training sequences, a dynamic phase adjustment method is applied to phase adaptive communication work with two ends not being fixed IO channels, stability of IO channel communication is improved, and adaptive adjustment on eye pattern interval changes caused by clock frequency, a printed circuit board (PCB) production process and FPGA internal placement and routing can be achieved.

Description

technical field [0001] The invention relates to the communication field, in particular to a debugging method and system for an IO channel between FPGA chips. Background technique [0002] With the rapid development of the Internet, the bandwidth of network system security products is increasing, and a single software platform can no longer meet the demand. More and more architectures are processed by software platforms and FPGA (Field-programmable gate array, field-programmable gate array) hardware platforms. High-speed network data is limited by the logic resources and IO interface resources of a single FPGA chip, and the solution of building a large-scale hardware platform with multiple FPGAs is gradually emerging. [0003] In the communication application of IO interconnection lines between multiple FPGA chips, the stability of the IO channel is the prerequisite for the correct operation of the system. The IO eye diagram interval of each FPGA chip will be affected by fac...

AI Technical Summary

Problems solved by technology

[0005] This dynamic phase debugging mode cannot be directly applied to IO debugging with FPGA devices at both ends

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