IO channel debugging method and system between fpga chips
A debugging method and a debugging system technology, applied in the communication field, can solve the problems that the dynamic phase debugging mode cannot be directly applied to FPGA device IO debugging, and achieve the effects of enhancing stability, reducing dependence, and improving work efficiency
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[0018] In the following, preferred embodiments of a method for debugging an IO channel between FPGA chips and a system for debugging an IO channel between FPGA chips related to the present invention will be described with reference to the accompanying drawings.
[0019] figure 1 It is a block diagram representing the general structure of the FPGA chip involved in the present invention; figure 2 It is a block diagram showing the connection relationship between the main control FPGA chip and the slave control FPGA chip involved in the present invention.
[0020] Such as figure 1 As shown, the FPGA chip 10 involved in the present invention includes a control unit 11, a sending unit 12 and a receiving unit 13, the sending unit 12 is used to send control signals and data to the outside, and the receiving unit 13 is used to receive external Control signals and data, etc., the control unit 11 is used to control the actions of the sending unit and the receiving unit.
[0021] refe...
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