Nonvolatile memory and operation method and manufacturing method thereof

Abstract

The invention discloses a nonvolatile memory which is of an intermittent type isolation structure and is provided with SONOS memory cell elements, and an operation method and a manufacturing method of the nonvolatile memory. On a semiconductor substrate provided with an array area, each isolation structure is provided with a plurality of intervals so that the intermittent type isolation structure can be formed, and source electrode wires can be distributed on the semiconductor substrate with the intervals. Therefore, due to the fact that the source electrode wires are not interrupted by the isolation structures, the number of potential barrier plugs not connected with the source electrode wires is largely reduced, and further the space occupied by the potential barrier plugs in the nonvolatile memory is saved.

Description

technical field [0001] The present invention relates to a non-volatile memory, more particularly to a non-volatile memory with a discontinuous isolation structure and SONOS memory cells, an operation method and a manufacturing method of the non-volatile memory. Background technique [0002] With the development of semiconductor integrated circuit manufacturing technology, the number of memory cells contained in non-volatile memory has been increasing, and the size of components has also been continuously reduced due to the increase in integration. [0003] However, no matter how small the size of the components is reduced, proper insulation or isolation is still required between the various memory cells in the non-volatile memory to ensure the stability of the memory cells and achieve good storage performance. characteristic. [0004] figure 1 A top view of an existing non-volatile memory array. figure 1 A part of the non-volatile memory array is shown, the memory array h...

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Problems solved by technology

[0005] However, due to the arrangement of the contact windows 122, 124 and the barrier plugs, it will cause difficulties in the process and reduce the yield of the product for the target of the miniaturized device size.

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