Multiple-grid transistor and manufacturing method thereof
A manufacturing method and transistor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as reducing gate oxide layer thickness, reducing short channel effect, source/drain influence potential energy, etc., to achieve The effect of short channel effect suppression
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[0032] The following excuses Figure 1-16 To illustrate a method for manufacturing a multi-gate transistor according to an embodiment of the present invention, wherein figure 1 , 3 , 5, 7, 9, 11, 14 are a series of top views, and figure 2 , 4 , 6, 8, 10, 12, 13, 15, 16 are a series of cross-sectional views, which respectively show the situation of the multiple gate transistor in different manufacturing stages.
[0033] Please refer to Figure 1-2 First, a semiconductor substrate 100 is provided, in which a plurality of isolation elements 102 are formed, and the plurality of isolation elements define a plurality of separated active regions 104 in the semiconductor substrate 100, so as to be disposed on and / or in the semiconductor substrate 100 a component (not shown). In one embodiment, the semiconductor substrate 100 is, for example, a bulk silicon substrate, and the isolation element 102 formed in the semiconductor substrate 100 is a shallow trench isolation (shallow tr...
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