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Multiple-grid transistor and manufacturing method thereof

A manufacturing method and transistor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as reducing gate oxide layer thickness, reducing short channel effect, source/drain influence potential energy, etc., to achieve The effect of short channel effect suppression

Active Publication Date: 2014-02-12
NAN YA TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when the gate length of the traditional bulk MOSFET is reduced, the source / drain will easily interact with the channel region and affect the potential energy in it.
Thus, transistors with shorter gate lengths may suffer from problems such as inability to control the channel switching state of the gate
[0003] The phenomenon of reduced gate-channel control ability of transistors with short gate length will lead to short-channel effect
However, increasing the doping concentration of the body, reducing the thickness of the gate oxide layer, and ultra-shallow source / drain junctions to reduce the short-channel effect are no longer satisfactory for traditional device structures such as using bulk silicon substrates.

Method used

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  • Multiple-grid transistor and manufacturing method thereof
  • Multiple-grid transistor and manufacturing method thereof
  • Multiple-grid transistor and manufacturing method thereof

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Embodiment Construction

[0032] The following excuses Figure 1-16 To illustrate a method for manufacturing a multi-gate transistor according to an embodiment of the present invention, wherein figure 1 , 3 , 5, 7, 9, 11, 14 are a series of top views, and figure 2 , 4 , 6, 8, 10, 12, 13, 15, 16 are a series of cross-sectional views, which respectively show the situation of the multiple gate transistor in different manufacturing stages.

[0033] Please refer to Figure 1-2 First, a semiconductor substrate 100 is provided, in which a plurality of isolation elements 102 are formed, and the plurality of isolation elements define a plurality of separated active regions 104 in the semiconductor substrate 100, so as to be disposed on and / or in the semiconductor substrate 100 a component (not shown). In one embodiment, the semiconductor substrate 100 is, for example, a bulk silicon substrate, and the isolation element 102 formed in the semiconductor substrate 100 is a shallow trench isolation (shallow tr...

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Abstract

The invention provides a multiple-grid transistor and a manufacturing method thereof. The transistor comprises a semiconductor substrate, a W-shaped groove, a semiconductor bridge, an oxide layer and a conducting layer. The W-shaped groove is formed in part of the semiconductor substrate and extends in a first direction. The semiconductor bridge extends in a second direction perpendicular to the first direction on the semiconductor substrate. The semiconductor bridge stretches across part of the W-shaped groove and is connected with the semiconductor substrate. The semiconductor bridge is provided with a flat top face and an arc bottom face. The oxide layer partially surrounds the flat top face of the semiconductor bridge and part of the arc bottom face. The conducting layer extends in the first direction and is formed on the semiconductor substrate and the oxide layer. The conducting layer surrounds the oxide layer and is partially filled into the W-shaped groove. According to the multiple-grid transistor and the manufacturing method thereof, combining of a channel and a grid electrode is improved, control of the grid electrode over channel potential energy is enhanced, short-channel effect restraining is facilitated, and miniature metal oxide semiconductor transistor performance is facilitated.

Description

technical field [0001] The present invention relates to semiconductor manufacturing, and in particular to a multi-gate transistor and a manufacturing method thereof. Background technique [0002] In the manufacture of ultra-large-scale integrated (ULSI) circuits, the manufacturing technology of metal-oxide semiconductor field effect transistors (MOSFETs) plays a decisive role. For more than ten years, the speed performance, circuit density and unit cost of devices have been improved by reducing the size of MOSFETs. However, when the gate length of the traditional bulk MOSFET is reduced, the source / drain will easily interact with the channel region to affect the potential energy therein. As such, transistors with shorter gate lengths may encounter problems such as being unable to control the channel switching state of the gate. [0003] The phenomenon of reduced gate-channel control capability of transistors with short gate lengths will lead to short-channel effects. Howev...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/423H01L29/78H01L21/28H01L21/336
CPCH01L21/28114H01L29/0611H01L29/4236H01L29/42376H01L29/66484H01L29/7831
Inventor 陈逸男徐文吉叶绍文刘献文
Owner NAN YA TECH