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Defect detection method for photolithographic process graph

A detection method and technology of lithography process, applied in the direction of micro-lithography exposure equipment, photolithography exposure device, etc., can solve the problems of long time consumption, cost increase, process efficiency decrease, etc., to achieve shortening time consumption, accurate search, and reduction The effect of cost of use

Active Publication Date: 2014-03-19
SHANGHAI HUALI MICROELECTRONICS CORP
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AI Technical Summary

Problems solved by technology

This scheme has high correction accuracy, but it takes considerable time to simulate the imaging situation of all mask images
[0008] The layout design-friendliness detection method in the lithography process provided in the above-mentioned prior art can detect various pattern defects and process hotspots, but it takes a long time to perform the OPC process on the entire lithography target pattern, making the process efficiency Falling, rising costs

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  • Defect detection method for photolithographic process graph
  • Defect detection method for photolithographic process graph
  • Defect detection method for photolithographic process graph

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Embodiment Construction

[0021] The specific embodiment of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0022] Such as figure 2 shown, combined with Figures 3A-3F , the layout design friendliness detection method in the photolithography process provided by an embodiment of the present invention includes the following steps:

[0023] Step S20, transforming the design target pattern data into a photolithography target pattern.

[0024] Specifically, the design target graph such as Figure 3A As shown, in this step S20, the design target graphic data is converted into a lithographic target graphic, which includes cleaning of small grooves or protrusions, etc., and the converted lithographic target graphic is as follows Figure 3B shown.

[0025] Step S21 , sequentially performing the first optical proximity effect correction and the first process deviation graphic simulation on the lithography target pattern.

[0026] Specifically...

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Abstract

The invention relates to a friendly detection method for a layout design in a photolithographic process. The friendly detection method comprises the following steps: converting designed target graphic data into a photolithographic target graph; sequentially carrying out primary optical proximity effect correction and primary process deviation graph simulation on the photolithographic target graph; carrying out primary process hot spot detection on the photolithographic target graph; if finding out at least one potential process hot spot by adopting the primary process hot spot detection, respectively carrying out secondary optical proximity effect correction and second time of secondary process deviation graph simulation on the photolithographic target graph close to each potential process hot spot; and carrying out secondary process hot spot detection on each detection region according to a result of the secondary process deviation graph simulation. The detection regions correspond to the potential process hot spots one by one and are generated according to the positions of the potential process hot spots. According to the method, the consumed time of friendly detection of the layout design in the photolithographic process can be shortened and the rapid and accurate finding of the process hot spots is realized; the utilization cost of software and hardware is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor processing and manufacturing, and more specifically, to a method for detecting pattern defects in a photolithography process. Background technique [0002] Photolithography is the main process in the manufacture of integrated circuits. It mainly realizes the transfer of the pattern on the mask plate to each layer of material on the silicon surface. The mask image is equivalent to an obstacle on the propagation path for light waves, so that the lithography related to the mask image is obtained on the silicon wafer. graphics. [0003] Due to design defects or limitations of resolution enhancement technology, the circuit on the wafer may have defects such as pinch off, bridging, and poor contact of holes. The area that may cause these defects in the layout is called the hot spot area of ​​the lithography process. It may affect the performance of the final circuit or even cause the failure of ...

Claims

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Application Information

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IPC IPC(8): G03F7/20
Inventor 王伟斌季亮魏芳张旭昇
Owner SHANGHAI HUALI MICROELECTRONICS CORP