United simulation tool suitable for multi-type CPU

A co-simulation and tool technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve problems such as increasing work complexity and workload, and achieve the effect of simplifying work and improving work efficiency

Active Publication Date: 2014-03-26
SHANGHAI HUAHONG INTEGRATED CIRCUIT
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Problems solved by technology

Usually for a BUG, ​​the above process will be repeated many times, and the work of corresponding the waveform to the assembly code in the above process is done manually, which adds a lot of unnecessary workload to the engineers
At the same time, since the work at the level of software-hardware interaction covers knowledge of both software and hardware, this puts a lot of burden on engineers from different backgrounds and virtually increases the complexity of the work

Method used

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  • United simulation tool suitable for multi-type CPU

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Embodiment Construction

[0014] As shown in the accompanying drawings, the co-simulation tool applicable to multiple types of CPUs includes: an ELF file interpreter, an instruction set disassembler, a waveform file interpreter, a waveform display, and a debugger user interface. The co-simulation tool has the function of displaying the graphical interface (that is, the user interface of the debugger), the function of displaying the waveform, and the function of bidirectional automatic correlation between the waveform and the kernel assembly instruction code. The co-simulation tool supports multiple types of CPU cores, such as C51 and ARM; the CPU core type can be selected through the debugger user interface. The co-simulation tool supports floating and embedding of each sub-window in the multi-document view.

[0015] Software test code is the software code written by software testers for further debugging of the circuit. The software test code is compiled by a compiler based on different kernels to ge...

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Abstract

The invention discloses a united simulation tool suitable for a multi-type CPU. The united simulation tool comprises a ELF file interpreter for extracting debugging information and data areas in ELF files, an instruction set disassemble for converting the debugging information and instructions in the inside into kernel assembly instruction codes of corresponding kernel instruction sets, a waveform file interpreter for reading and analyzing VCD files, interpreting multi-channel digital signal waveform information in the VCD files to generate waveform output modes and loading the waveform output modes into an internal memory, a waveform oscilloscope for processing interpreted multi-channel digital signal waveform information stored in the internal memory, a debugger user interface for displaying the kernel assembly instruction codes and multi-channel digital signal waveforms through respective windows and achieving automatic mutual correspondence between the multi-channel digital signal waveforms and the kernel assembly instruction codes. The united simulation tool can effectively improve the verification work efficiency.

Description

technical field [0001] The invention relates to a co-simulation tool suitable for multi-type CPUs (central processing units). Background technique [0002] With the continuous development of integrated circuit technology and the continuous deepening of integrated circuit (IC) application fields, the complexity and performance complexity of IC design have been substantially improved compared with before, which puts forward the verification scheme for chip design companies and chip application manufacturers. higher requirements. [0003] For the design of a circuit with a core, the traditional method is to simulate the hardware code on a large server or workstation, and the simulation result is reflected on the graphical interface in the form of a waveform. In this process, the software or hardware engineer compiles the software code and provides it to the verification engineer as an input file for hardware simulation. This verification method locates hidden defects (hereina...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 丁颖张万强
Owner SHANGHAI HUAHONG INTEGRATED CIRCUIT
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