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Differential output circuit and semiconductor device

A technology of output circuit and differential pair, which is applied in the direction of semiconductor devices, electric solid devices, amplifiers with semiconductor devices/discharge tubes, etc., can solve the problem of low durability and achieve high reliability

Active Publication Date: 2018-04-13
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, although low-voltage transistors can operate at high speeds, their durability against overvoltages applied to elements is not high

Method used

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  • Differential output circuit and semiconductor device
  • Differential output circuit and semiconductor device
  • Differential output circuit and semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment approach

[0117] figure 1 Shown is a circuit diagram of a differential output circuit related to the first embodiment. figure 1 The differential output circuit in has regulators RG1 and RG2, buffer circuits BUF1 and BUF2, output terminals OUT and OUTB, current source I1, NMOS transistors MN1-MN6, and resistance elements R1-R4.

[0118] The voltage regulator RG1 steps down the voltage of the power supply VDDH (for example, 3.3V or 2.5V) and outputs the power supply VDDM (for example, 1.8V). The voltage regulator RG2 steps down the voltage of the power supply VDDM and outputs the power supply VDDL (for example, 1.0V).

[0119] The buffer circuits BUF1 and BUF2 are driven by the power supply VDDL, buffer the input signals IN and INB and supply them to the gates of the NMOS transistors MN1 and MN2 respectively. In this embodiment, the input signals IN and INB are input signals in opposite phases of each other.

[0120] The NMOS transistors MN5 and MN6 constitute a current mirror, and a c...

Deformed example 1

[0137] image 3 Shown is a circuit diagram of Modification 1 of the differential output circuit related to the first embodiment. image 3 in, with figure 1 The same symbols represent the same content, so repeated descriptions will not be repeated here. The back gates of the NMOS transistors MN3 and MN4 are commonly connected to the back gates of the NMOS transistors MN1 and MN2 through the resistance element R10, and are respectively connected to the respective sources of the NMOS transistors MN3 and MN4 through the resistance elements R11 and R12.

[0138] Next, a semiconductor device in which the differential output circuit in Modification 1 is formed will be described. Figure 4 Shown is a cross-sectional view of the structure of a semiconductor device related to Modification 1. FIG. Figure 4 in, with figure 2 The same symbols represent the same content, so repeated descriptions will not be repeated here. Figure 4 The semiconductor device shown has a replacement f...

Deformed example 2

[0142] FIG. 5 is a circuit diagram of Modification 2 of the differential output circuit related to the first embodiment. Figure 5, with figure 1 The same symbols represent the same content, so repeated descriptions will not be repeated here. One end of the resistance element R15 is connected to the power supply VDDM, and the other end is connected to the gates of the NMOS transistors MN3 and MN4. The gate of the PMOS transistor MP2 is connected to the power supply VDDM, the source is connected to the node N2, and the drain and back gate are connected to the gates of the NMOS transistors MN3 and MN4.

[0143] In the differential output circuit having the above configuration, when the power supply VDDM is 1.8V, a bias voltage is supplied from the power supply VDDM to the gates of the NMOS transistors MN3 and MN4 via the resistance element R15. On the other hand, when the power supply VDDM (0V) is turned off, the PMOS transistor MP2 is turned on, and a bias voltage is supplied ...

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PUM

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Abstract

A highly reliable circuit is realized using the transistors having a lower withstand voltage. There are provided a differential pair including a first and a second transistor which respectively receive input signals having mutually reversed phases; a third and a fourth transistor respectively cascode-coupled to the first and the second transistor, and having the same conductivity type as the first and the second transistor; a first and a second output terminal coupled to respective drains of the third and the fourth transistor; and a voltage divider circuit which divides an intermediate potential between respective potentials of the first and the second output terminal and supplies the divided potential to gates of the third and the fourth transistor.

Description

technical field [0001] The present invention relates to a differential output circuit and a semiconductor device, such as a technology for supplying bias voltage to transistors in the differential output circuit and the semiconductor device. Background technique [0002] When data is transmitted between LSI internal circuits, between LSIs, between printed circuit boards, and between devices constituting electronic equipment, there is an increasing demand for higher speeds. In response to these requirements, low-voltage transistors are used in the output circuit that outputs differential signals during data transmission to achieve higher speed and lower power consumption. However, although low-voltage transistors can operate at high speeds, they do not have high durability against overvoltages applied to the elements. [0003] Therefore, as disclosed in Patent Document 1, an output circuit has: a differential pair composed of a first transistor and a second transistor respec...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03F3/45
CPCG05F3/205G05F3/24H03F1/523H03F3/45188H03F3/45632H04L25/0272H04L25/028H01L27/0207H01L27/0629H01L29/0653H03F3/45179
Inventor 三石昌史光明雅泰砂入崇二
Owner RENESAS ELECTRONICS CORP