Chip packaging structure with cavity and packaging method thereof

Abstract

The invention discloses a chip packaging structure with a cavity and a packaging method thereof. The chip packaging structure comprises a chip, a substrate, a pin frame, a wire and a plastic package body, wherein the lower surface of the chip is arranged on the substrate; the chip is connected with the pin frame by the wire; the plastic package body is used for packaging the chip, the pin frame and the substrate; the pin frame is exposed out of the bottom surface or the side face of the plastic package body; the cavity is arranged between the plastic package body and the chip, so that one surface which does not contact with the plastic package body at least exists in the side face and the upper surface of the chip. The cavity is arranged between the plastic package body and the chip, so the sensitive part of the surface of the chip does not contact with the plastic package body, the sensitive part is not covered by the plastic package body, and the stress influence on the internal structure of the chip, which is caused by the packaging structure is reduced; the chip packaging structure further comprises a through hole which is beneficial for the ventilation and the heat radiation of the chip; the packaging structure has the characteristics that the manufacturing process is simple and advanced, the size is relatively small, the heat radiation is excellent and the like, and the reliability in the using process of the electronic chip is improved.

Description

technical field [0001] The invention relates to semiconductor packaging technology, in particular to a chip packaging structure with a cavity and a packaging method thereof. Background technique [0002] In today's consumer electronics, automotive electronics, and the more demanding aviation, aerospace, and military industries, the requirements for electronic chips and other products with features such as multi-function, high performance, miniaturization, light weight, portability, and low cost are increasing. come higher. Packaging these chips with I / O pins to make electronic products that meet various uses and requirements requires wafer-level chip-scale packaging (WL-CSP), multi-chip module (MCM) or three-dimensional system-level Packaging module (3D SiP module) and other modern microelectronic packaging technologies. The rapid development of modern microelectronic packaging technology is constantly changing people's work and lifestyle, and prompting the whole world to ...

AI Technical Summary

Problems solved by technology

Although the microelectronic packaging in the prior art provides protection to the chip in terms of electrical, thermal, optical and mechanical properties, it cannot meet the ever-increasing performance requirements and requirements for functions such as reliability, heat dissipation and power distribution at a certain cost. need

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