A Method of Combining Read Data in Image Distortion Correction Algorithm

An image distortion and correction algorithm technology, applied in the field of image processing, can solve the problems of low dynamic RAM access efficiency, inability to meet real-time processing, and many steps to read data, so as to achieve efficient access efficiency, meet real-time processing, and reduce hardware costs. desired effect

Active Publication Date: 2017-02-01
SUZHOU KEDA TECH
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Problems solved by technology

[0005] For this reason, the technical problem to be solved by the present invention is that there are too many steps for reading data, the access efficiency to dynamic RAM is not high, and the processing time is too long, which cannot meet the needs of real-time processing

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  • A Method of Combining Read Data in Image Distortion Correction Algorithm

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Embodiment Construction

[0018] After the video data enters the system, we first need to frame buffer the original image data. These data need to be stored in the DDR memory in the order of the data stream, and then generate the data reference position points required for each distortion correction according to the distortion distortion algorithm. , these reference points need to count the burst length and start address of the generated DDR. At the same time, in order to increase the access data efficiency of DDR and reduce the frequency of line-wrapping operations for data access, it is necessary to perform an operation similar to the access sequence rearrangement on the two lines of source image data in the previous calculation window and the two lines of source image data in the current calculation window , this operation needs to distinguish different calculation methods according to the different increase and decrease trends of the start row position of each DDR burst window in different quadrants...

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Abstract

The invention discloses a method for combining reading data in an image distortion correcting algorithm, wherein the image distortion correcting algorithm is a bilinear interpolation algorithm. A current point is subjected to interpolation operation according to a pixel value of a window where the current point is, and each row of pixels is provided with a plurality of continuous current points. The method is characterized in that some row of a plurality of current pixel data and the next operation row of a plurality of current points needed by the interpolation operation of the current point are read in a combining way. Based on the method, a real-time modifying function can be realized by using an FPGA (Field Programmable Gata Array) of an SPANTAN6 and a hardware platform of DDR2SDRAM with the monolithic data rate of 400MHz*16bit, under the condition that the polynomial resolution of barrel distortion distortion model with the HD (High-Definition) video 1080p30 data bit 16bit YUV 4:2:2 meet formulas: K3=0.7 and K5=0.5, so that the hardware platform is simplified.

Description

technical field [0001] The invention relates to a method for combining read data in an image distortion correction algorithm. It belongs to the technical field of image processing. Background technique [0002] In digital image processing, regarding the processing algorithm of high-definition video distortion and distortion, taking bilinear interpolation as an example, from the perspective of algorithm implementation, it needs 5 times the original image data stream to read and write from the cache, plus the same time point The data that needs to be involved in the calculation is very fragmented relative to its storage location in the cache. Therefore, most of the existing devices that implement this algorithm use platforms that support high-bandwidth DRAM interfaces or SSRAM interfaces, which will increase costs and power consumption, and some sacrifice processing effects to compensate memory. Get bandwidth problem. [0003] In the prior art, Chinese patent 201310395095.7...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04N19/80H04N19/156
Inventor 简礼宏章勇曹李军陈卫东
Owner SUZHOU KEDA TECH
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