Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Analog circuit fault diagnosis method based on cascade connection integrated classifier

A fault diagnosis and classifier technology, applied in the direction of instruments, measuring electricity, measuring electrical variables, etc., can solve problems such as difficult to distinguish

Inactive Publication Date: 2014-04-16
NAVAL AERONAUTICAL & ASTRONAUTICAL UNIV PLA
View PDF7 Cites 27 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

a) The fault diagnosis device uses a multi-classifier cascade model, firstly to solve the problem that it is difficult to distinguish between normal samples and early fault samples, that is, firstly, the characteristic samples of normal circuits and the samples of all fault circuits form two disjoint subsets, Using homomorphic integration technology to construct a support vector machine classifier, forming a level G 0 , used to distinguish between normal and faulty states; secondly, for faulty samples, the base classifiers of different algorithms are trained using heterogeneous integration technology, and then the classifiers are merged using the weighted voting algorithm to form a hierarchy G 1 , used to distinguish different fault states, this two-level structure forms a multi-category cascade reasoning idea

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Analog circuit fault diagnosis method based on cascade connection integrated classifier
  • Analog circuit fault diagnosis method based on cascade connection integrated classifier
  • Analog circuit fault diagnosis method based on cascade connection integrated classifier

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0007] Knowledge-based analog circuit fault diagnosis technology is essentially a pattern recognition and classification problem. Therefore, how to extract effective features of faults is a key technology and an important part of analog circuit fault diagnosis. At the same time, the ultimate purpose of extracting features is to construct a classifier for test samples and realize correct classification and identification of different fault types. Ultimately, to achieve this goal and complete the real realization of fault diagnosis, it is necessary to implement software for the algorithm.

[0008] In order to achieve the above object, method of the present invention is achieved like this:

[0009] 1. Optimal wavelet extraction of analog circuit fault feature information

[0010] The wavelet fault feature information extraction method as a signal processing is a current research hotspot. Wavelet analysis belongs to multi-resolution analysis, which is a fine time-frequency analys...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses an analog circuit fault diagnosis method and an implementation method of the analog circuit fault diagnosis method. The content includes the first part of analog circuit fault feature information extraction, the second part of fault classifier construction, and the third part of implementation of algorithm software. The analog circuit fault diagnosis method includes the following steps of constructing a fault feature information base, selecting an optimal mother wavelet through an information entropy maximizing principle, conducting wavelet decomposition on response nodes of a measured circuit, extracting the optimal feature of the measured circuit, conducting dimensionality reduction on the fault features through principal component analysis, conducting fault classification and intelligent diagnosis, constructing a fault diagnosis device according to the obtained fault feature information and through a multi-classifier cascade connection model and the classifier integration technology so as to recognize existing faults and causes of the faults, and conducting specific implementation on the algorithm through a C#.NET platform and through combination with the Weka software. The diagnosis method and the implementation method have the advantages of being high in fault diagnosis performance, wider in diagnosis range, higher in algorithm robustness and higher in interpretability.

Description

technical field [0001] The invention relates to a fault diagnosis method of an analog circuit and its realization. Background technique [0002] Fault diagnosis of analog circuits began in the 1960s, and its theoretical research started from the solvability of network element parameters. However, due to its unique difficulties such as diversity of fault states, tolerance of element parameters, insufficient information and Due to the complexity of the structural model, etc., the development of research on fault diagnosis of analog circuits is relatively slow, and its testing and fault diagnosis has always been a problem that plagues the circuit testing industry. After the 1990s, with the development of artificial intelligence technology, fuzzy theory, wavelet technology and some machine learning methods have been applied in this field and achieved good results, but they all have one-sidedness and have no effect on solving actual analog circuit faults. There is still a certai...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/3163
Inventor 史贤俊周绍磊廖剑肖支才戴邵武张文广王朕张树团秦亮
Owner NAVAL AERONAUTICAL & ASTRONAUTICAL UNIV PLA
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products