Universal error-tolerant and error-correcting circuit and its applied decoder and triple-mode redundant circuit

An error correction circuit and decoder technology, applied in the field of integrated circuits, can solve problems such as lack of strong error correction capability and increased bit error rate

Active Publication Date: 2017-01-04
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] However, the hardware complexity brought by triple-mode redundancy is at least twice the complexity of the original module. Secondly, when the triple-mode redundancy module itself has errors, the output bit error rate will increase significantly, and there is no strong correction Wrong ability

Method used

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  • Universal error-tolerant and error-correcting circuit and its applied decoder and triple-mode redundant circuit
  • Universal error-tolerant and error-correcting circuit and its applied decoder and triple-mode redundant circuit
  • Universal error-tolerant and error-correcting circuit and its applied decoder and triple-mode redundant circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0058] see figure 2 , which is a schematic structural diagram of a general error-tolerant and error-correcting circuit provided by the present invention.

[0059] The general error-tolerant and error-correcting circuit provided in this embodiment is characterized in that it includes: an error-tolerant and error-correcting unit 100 implemented by logic gates;

[0060] The digital input signals of the error-tolerant and error-correcting unit 100 are respectively I 0 , I 1 ..., I 2k-1 , I 2k ; The digital output signals of the error-tolerant and error-correcting unit are respectively O 0 , O 1 ...,O k-2 , O k-1 ; The digital input signal and the digital output signal belong to the set {0,1}; wherein, k is a positive integer;

[0061] The error-tolerant and error-correcting unit is used when k=1, if I 0 =I 1 , then O 0 =I 0 , otherwise O 0 =I 2 ; When k>1, if O k-2 =I 2k-1 , then O k-1 =I 2k-1 , otherwise O k-1 =I 2k .

[0062] In order to enable those skille...

Embodiment 2

[0078] see Figure 5 , which is a schematic diagram of Embodiment 2 of the error-tolerant and error-correcting circuit provided by the present invention.

[0079] When k=1 in the error-tolerant and error-correcting unit provided by the present embodiment, the corresponding three digital input signals are respectively: I 0 , I 1 , I 2 ; Corresponding to a digital output signal: O 0 ;

[0080] The error-tolerant and error-correcting unit includes: a first AND gate A1, a first OR gate B1, a second AND gate A2, and a second OR gate B2;

[0081] The two input signals of the first OR gate B1 are respectively I 0 , I 1 ;

[0082] The two input signals of the first AND gate A1 are respectively I 0 , I 1 ;

[0083] An input signal I of the second AND gate A2 2 , the output signal of the first OR gate B1 is used as another input signal of the second AND gate A2;

[0084] The output signal of the second AND gate A2 and the output signal of the first AND gate A1 are used as tw...

Embodiment 3

[0088] Figure 5 Shown is the implementation of the circuit when k=1, combined below Figure 6 Introduce the circuit implementation when k=3.

[0089] see Figure 6 , which is a schematic diagram of Embodiment 3 of the error-tolerant and error-correcting circuit provided by the present invention.

[0090] In this embodiment, when k=3 in the error-tolerant and error-correcting unit, the corresponding seven digital input signals are respectively: I 0 , I 1 , I 2 , I 3 , I 4 , I 5 , I 6 ; Corresponding to three digital output signals are: O 0 , O 1 , O 2 ;

[0091]The error-tolerant and error-correcting unit includes three error-tolerant and error-correcting subunits, which are respectively the first error-tolerant and error-correcting subunit 100a, the second error-tolerant and error-correcting subunit 100b, and the third error-tolerant and error-correcting subunit 100c; each error-tolerant and error-correcting subunit Each unit corresponds to three digital input si...

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Abstract

The invention provides a general error-tolerant and error-correcting circuit and its applied decoder and triple-mode redundant circuit, wherein the general-purpose error-tolerant and error-correcting circuit includes: an error-tolerant and error-correcting unit realized by logic gates; a digital error-tolerant and error-correcting unit The input signals are I0, I1..., I2k-1, I2k respectively; the digital output signals of the error-tolerant and error-correcting unit are O0, O1..., Ok-2, Ok-1 respectively; the digital input signals and digital output signals belong to the set {0, 1}; wherein, k is a positive integer; the error-tolerant and error-correcting unit is used for when k=1, if I0=I1, then O0=I0, otherwise O0=I2; when k>1, if Ok‑2=I2k ‑1, then Ok‑1=I2k‑1, otherwise Ok‑1=I2k. Since the logical relationship between the input and the output is uniquely determined, the error-tolerant and error-correcting circuit can only be realized by logic gates, and there are many specific implementation modes, as long as the uniquely determined logical relationship of the present invention is satisfied between the input and the output That's it. Therefore, the error-tolerant and error-correcting circuit provided by the present invention has universal versatility.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a universal error-tolerant and error-correcting circuit and a decoder and a triple-mode redundant circuit applied thereto. Background technique [0002] With the rapid development of electronic information, the utilization rate of electronic chips is getting higher and higher, but soft errors or hard errors will also occur in the use of electronic chips. [0003] Soft error can be understood as the logic error of the tube, such as changing from 0 to 1, or from 1 to 0. [0004] A hard error can be understood as a permanent logic error of the tube. [0005] However, some fields have extremely high requirements for the precision of electronic chips, such as aerospace, medical and precision instruments and other fields. Both soft and hard errors in electronic chips can have serious consequences. [0006] A fault-tolerant technology widely used in the prior art is Tripl...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/003
CPCG06F11/187H03K19/23G06F11/183H03M13/6508H03M13/27H03M13/1105H03M13/43H04L49/557
Inventor 唐样洋张臣雄
Owner HUAWEI TECH CO LTD
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