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Systems and methods for optimizing current density in cmos-integrated mems capacitive devices

A device and current technology, applied in the field of current routing, can solve problems such as the increase of shunt parasitic capacitance of MEMS capacitors

Active Publication Date: 2016-04-06
AAC TECH PTE LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, such a metal shield increases the shunt parasitic capacitance of the MEMS capacitor caused by the metal layers in the MEMS device and the interlayer dielectric between the shield and the device.

Method used

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  • Systems and methods for optimizing current density in cmos-integrated mems capacitive devices
  • Systems and methods for optimizing current density in cmos-integrated mems capacitive devices
  • Systems and methods for optimizing current density in cmos-integrated mems capacitive devices

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Embodiment Construction

[0017] This topic deals with current splitting and routing techniques to distribute current evenly among multiple layers of a device to achieve a high figure of merit. This current splitting can allow the use of relatively narrow interconnects and feedlines while maintaining a high quality factor (Q). Furthermore, since the device has a fixed thickness, Q and Cmin cannot be optimized independently, so the design process can also effectively optimize Q and Cmin together. Thus, the present subject matter can be advantageously used for 1) optimization of Cmin and / or parasitic capacitance; 2) maximization of Q; 3) maximization of equal distribution of current based on material volume and engagement of current paths; and 4) Minimization of the temperature coefficient of uneven current division due to mis-design or volume mismatch. Therefore, the present subject matter can help realize RFMEMS devices with high quality factors on lossy substrates. In addition, parasitics associated...

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Abstract

The present subject matter relates to the use of current splitting and routing techniques to distribute current uniformly among the various layers of a device to achieve a high Q-factor. Such current splitting can allow the use of relatively narrow interconnects and feeds while maintaining a high Q. Specifically, for example a micro-electromechanical systems (MEMS) device can comprise a metal layer comprising a first portion and a second portion that is electrically separated from the first portion. A first terminus can be independently connected to each of the first portion and the second portion of the metal layer, wherein the first portion defines a first path between the metal layer and the first terminus, and the second portion defines a second path between the metal layer and the first terminus.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of US Provisional Patent Application No. 61 / 520,283, filed June 7, 2011, the disclosure of which is hereby incorporated by reference in its entirety. technical field [0003] The subject matter disclosed herein relates generally to the design of microelectromechanical systems (MEMS) capacitive devices. More particularly, the subject matter disclosed herein relates to current routing within material layers of MEMS devices. Background technique [0004] Radio frequency (RF) MEMS devices built on low-resistivity silicon wafers using standard complementary metal-oxide-semiconductor (CMOS)-compatible fabrication processes are prone to high substrate losses due to the underlying low-resistivity silicon. To deal with this problem, metal shields are often used to isolate the RF circuitry from the lossy substrate in these cases. However, such a metal shield increases the shunt parasitic cap...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): B81B3/00H01G5/16H01H59/00
CPCH01G5/16H01G5/18H01H59/0009Y10T29/43
Inventor 亚瑟·S·莫里斯三世萨拉瓦娜·纳塔拉詹达娜·德雷乌斯
Owner AAC TECH PTE LTD