Parallel and serial data converting circuit based on FPGA

Abstract

The invention discloses a parallel and serial data converting circuit based on an FPGA. The parallel and serial data converting circuit is composed of a data output selector and pulse generation units capable of generating pluses. The data output selector is a one-out-N selector. Each pulse generation unit is composed of a time-delay unit, an inverter and an AND gate. The time-delay unit is enabled to be precise and controllable using the locating and wiring constraint technology. The parallel and serial data converting circuit provided by the invention can achieve a serial transmission speed of GHz, is achieved using the FPGA design, and has high accuracy, strong versatility and applicability.

Description

technical field [0001] The invention belongs to a parallel-serial data conversion circuit, in particular to an FPGA-based parallel-serial data conversion circuit with a transmission speed of up to 1 gigahertz. Background technique [0002] The FPGA-based parallel-serial data conversion circuit is used to convert multi-bit parallel data into one-bit serial data. [0003] At present, the parallel-to-serial data conversion in the FPGA is mainly realized through the hard core of the parallel-to-serial data conversion. The hard core of parallel serial data will only appear in mid-to-high-end FPGAs, thus limiting the application of low-end FPGAs. Moreover, due to the limitation of the number of hard cores, when the demand for parallel-to-serial data conversion is large, it needs to use a dedicated chip to realize it, which increases the cost and brings great inconvenience to the circuit design due to the increase of pins. Contents of the invention [0004] The purpose of the p...

AI Technical Summary

Problems solved by technology

The hard core of parallel serial data will only appear in mid-to-high-end FPGAs, thus limiting the application of low-end FPGAs

Moreover, due to the limitation of the number of hard cores, when the demand for parallel-to-serial data conversion is large, it is necessary to use a dedicated chip to realize it, which increases the cost and brings great inconvenience to the circuit design due to the increase of pins.

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