Method for manufacturing display panel

Abstract

The embodiment of the invention discloses a method for manufacturing a display panel provided with a light doped drain electrode structure thin film transistor matrix. The method for manufacturing the display panel comprises the steps that a semiconductor pattern of a preset shape is firstly formed on a substrate, a dielectric layer covering the semiconductor pattern is formed on the substrate, a metal layer is formed on the dielectric layer, a light resistance pattern with the size smaller than that of the semiconductor pattern is formed, over the semiconductor pattern, on the metal layer, and the metal layer is etched so that a grid electrode with the size smaller than that of the light resistance pattern can be formed; the light resistance pattern serves as a mask, high-concentration ion doping is conducted on the portions which are not covered with the light resistance pattern so that a heavily doped region can be formed; the light resistance pattern is removed, the grid electrode serves as a mask and low-concentration ion doping is conducted on the heavily doped region and a region, covered with the grid electrode, of the semiconductor pattern so that a light doped region can be formed.

Description

technical field [0001] The present invention relates to a method for manufacturing a display panel, in particular to a method for manufacturing a display panel with a lightly doped drain (Lightly Doped Drain, LDD) structure thin film transistor (Thin Film Transistor, TFT). Background technique [0002] Most of the existing methods for fabricating TFTs with LDD structures by self-alignment require repeated etching of the gate metal layer of the TFTs. The first etch of the gate metal layer defines the location of heavily doped regions within the semiconductor layer. A second etch of the gate metal layer defines the location of lightly doped regions within the semiconductor layer. Therefore, the size of the LDD structure formed by repeatedly etching the gate metal layer is affected by multiple etching errors, and its precision is low. Moreover, multiple times of etching also increases the number of photomasks and increases the manufacturing cost of the display panel. [0003...

AI Technical Summary

Problems solved by technology

Therefore, the size of the LDD structure made by repeated etching of the gate metal layer is affected by multiple etching errors, and its precision is low.

Moreover, multiple etching also increases the number of photomasks and increases the manufacturing cost of the display panel

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