NCS algorithm parallelization method based on multiple FPGA platforms
An algorithm and platform technology, applied in the field of parallelization of NCS algorithms, can solve the problems of low computing efficiency, high memory read speed and high processor performance requirements, and achieve the effect of improving efficiency
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Example Embodiment
[0022] The solution of the present invention will be described in detail below with reference to the drawings.
[0023] This embodiment is based on a multi-FPGA platform composed of 4 Xilinx XC6VLX550T FPGA chips, such as figure 1 As shown, each FPGA chip is designed with a heterogeneous multi-core prototype chip based on 4*4 2D mesh architecture with a data bit width of 64 bits. The 4*4 2D mesh architecture is expanded to 16*16 2D mesh through the high-speed channel between FPGAs. Architecture. Each FPGA chip integrates 4 arithmetic cluster units and 1 transpose cluster unit to complete a large number of calculations and transpositions in the NCS algorithm. The overall software process of the NCS algorithm is as follows figure 2 Shown. In the following, combined with the NCS algorithm, taking the image size of 32M Byte as an example, the pipeline method and the task parallelization method are described in detail.
[0024] The method for parallelizing NCS algorithms based on mul...
PUM
Abstract
Description
Claims
Application Information
- R&D Engineer
- R&D Manager
- IP Professional
- Industry Leading Data Capabilities
- Powerful AI technology
- Patent DNA Extraction
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.
© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap